Design Techniques Of High Performance CMOS Mixer

With the development of personal communication systems and digital TV broadcast, the requirement of small, low power and low cost transceivers is fast increasing. The general approach taken towards this goal is to move towards higher levels of integration. Due to the requirement of the integration and power dissipation, CMOS technology is the only choice for all digital circuits which excess 75 percent of transceiver ICs. To implement RF front ends using CMOS technology is the necessary way to realize higher levels of integration. With the development of CMOS processes, a maximum cutoff frequency above 200 GHz is observed for the 50-nm NMOS device, which provides feasibility for implementing RF front ends using CMOS technology. However, CMOS process technology provides smaller transconductance, poor frequency response and higher noise comparing with other technology. More and more research activities focus on realizing high performance CMOS RF font ends. In this paper, a high performance CMOS mixer optimization technique is investigated and the mixer in digital TV tuner IC is designed by the technique.Modeling the performance of circuit is one of the important techniques in the CMOS RFICs optimization. The scaling of CMOS results in that the former performance models can not accurately predict the performances of the actual CMOS mixer. Three performance models of CMOS mixer are corrected in this paper. Firstly, the mixer's mechanism with practical local oscillator (LO) signals is investigated in detail. Circuit behaviors with four different kinds of LO signals are described by math model. Four correctional equations of mixer voltage conversion gain are derived. Secondly, a time domain method is adopted in analyzing process of mixers nonlinearity. Based on the basic theory of circuit nonlinearity, a new analytical nonlinearity model of CMOS mixers is derived with detailed consideration of the MOSFETs nonlinearity. Finally, the noise behavior of Deep Submicron CMOS mixers is investigated. An analytical noise figure model of the mixers is derived. All the performance models presented in this paper are verified by means of simulation. With the help of these models, a mixer in digital TV tuner IC is designed by traditional design method. The circuit is processed in 0.25μm CMOS technology.The"try-and-error"design technique, which is very time-consuming in the design of RFICs, can not realize the better circuit optimization. So the common design technique brings CMOS mixer more design cycles and higher design cost. An equation-based design method of CMOS mixers sizing optimization using genetic algorithms is presented. A new constrains processor with searching space limiter and penalty function is used in the optimization process. The optimized design parameters and performances satisfying specifications are fast acquired through the method. Based on the measurement results of the fabricated mixer circuit, another mixer integrated in digital TV tuner IC is designed through the optimization method. The optimized mixer is verified by simulation and ready to tapeout.