Power optimization of asynchronous pipelines using conditioning and reconditioning based on a three-valued logic model

Asynchronous circuit design has long been considered a suitable alternative to synchronous design due to its potential for achieving lower power consumption, higher robustness to process variations, and faster throughput. The lack of commercial CAD tools, however, has been a major obstacle for its wide-spread adoption. Although there is no central clock, the use of handshaking protocols in asynchronous circuits often introduces excessive switching activity which then translates to high power consumption. This work is about reducing unnecessary switching activity and automatically optimizing power consumption of asynchronous circuits. Our focus is on circuits synthesized by a recently commercialized high-throughput asynchronous ASIC CAD flow called Proteus..;We propose a formal framework based on three-valued logic in which we model the conditional communication primitives of asynchronous circuits as three-valued operators. Using this framework, we introduce two systematic power reduction techniques for asynchronous circuits:conditioning (adding conditional communication) and reconditioning (moving conditional communication primitives).;To demonstrate an application of conditioning, an automatic method is introduced for the adoption of operand-isolation in asynchronous circuits using commercial synchronous CAD tools. Our experimental results show that for a 32-bit ALU, we achieve an average of 53% power reduction for about a 4% increase in area with no impact in performance.;An integer linear program (ILP) formulation is presented for the reconditioning problem. Our experimental results show that our ILP can be solved in reasonable time for medium size circuits and can achieve up to 80% power improvement. For larger circuits when the ILP formulation is not tractable, a fast heuristic algorithm is provided. Our experimental results show that our heuristic algorithm can still significantly reduce power and can achieve close-to-optimal results.;Finally, a method for formal verification of asynchronous circuits based on the three-valued logic model is presented. In particular, we show how our three-valued logic model can enable the use of powerful commercial synchronous formal verification tools for equivalence check of asynchronous circuits.