Design Of 10 Bit 30 MS/s Low Power Consumption SAR ADC

As a classical structure of ADC,SAR ADC has gained widely attention and developed fast in recent years for its advantages as simple structure,low power and good compatibility with digital circuits.It's a very suitable choice for medium precision medium speed applications.And due its working characteristics,its power is related to sampling rate.So it is very suitable for some medical apparatus which do not need continuous sampling or whose input single does not change significantly,and it is widely used in industry.This main work is to achieve a medium precision medium speed and low power SAR ADC.Firstly,according to the core journals the current status of research and development of SAR ADC is surmised,and then the ways to realize a low power ADC are introduced and been comprehensively summarized and compared.The schematic design includes DAC design,comparator design,asynchronous logic design,switch design and digital error calibration design.Capacitors digital to analog convertor(DAC)and monotone switching method are chosen and improved novelty to stop VCM from falling to ground.The structure of DAC has been improved,non-binary redundancy is formed by splitting the most significant digit(MSB)and recombining those capacitors with pervious binary capacitors.Low power comparator is chosen,offset calibration circuit and metastable state detection circuit are designed.Asynchronous self-control circuit is designed to avoid high speed outer clock.The circuits of SAR ADC are implemented with SMIC 180nm CMOS process.After physical layout design which occupies 340?m×370?m,the post-simulation results show the SNDR of the proposed ADC is 50dB and the SFDR is 58.4dB,thus the ENOB is 8.02 bit,and the INL and DNL are both less than 1 LSB,while the analog and digital power is 1.8V and sample rate is 30MS/s.Consequently,the results satisfy the design requirements.