Cell State Remapping And LDPC Decoding Optimization Based On Flash Error Characteristics

NAND flash is a widely used non-volatile storage medium.With the continuing semiconductor process scaling and the introduction of muti-level storage technology,the density of NAND flash has been greatly increased.However,the aggressive increase of NAND flash memory density comes at the cost of shrunk lifetime and reduced reliability.In order to ensure flash reliability,this thesis proposes a method of combining positive prevention and efficient correction,and studies how to reduce the bit error rate of flash memory from the two aspects of error prevention before data writing and error correction during data reading.Program interference errors and retention errors have been recognized as the two main types of NAND flash errors,which are both closely related to the flash state.Since NAND flash cells in the state that holds lower threshold voltage are less likely to cause program interference and retention errors,existing schemes increase the ratio of cells in the erased state to reduce the raw bit error rate.However,they only focus on one state of flash memory,and do not consider the partial counteraction between these two errors.Based on the error characteristics of flash memory,this thesis proposes a Cell State Remapping(CeSR)scheme to preprocess the raw data from the perspective of error prevention.CeSR adopts different flipping schemes for different written data in order to achieve the least error-prone data pattern,thus reducing the probability of data error and the raw bit error rate of flash memory.Evaluation shows that the proposed CeSR scheme can reduce the raw bit error rates of hot and cold data by up to 20.50% and 85.13%,respectively,compared with the best data preprocessing work.With the increase of flash error rate,low density parity check code(LDPC code)is used for flash error correction.However,the complex LDPC decoding process will lead to significant decoding latency,and the LDPC decoding success rate will be affected when the raw bit error rate of flash memory is high.This thesis proposes an Assisted LDPC decoding scheme from the perspective of error correction.Assisted LDPC decoding scheme leverages the error characteristics and data pattern to assist LDPC decoding,thus improving the decoding success rate and decreasing the number of decoding iterations(reducing the decoding latency).The Assisted LDPC decoding scheme can couple with CeSR to further ensure flash reliability,and can also be used independently.When coupled with CeSR,evaluation shows that the Assisted LDPC decoding scheme can increase the decoding success rate by up to 97% and decrease the average decoding iteration number by up to 73.88%,compared with the traditional LDPC decoding scheme.