Research On MD5 And SHA-256 Algorithm Realize With FPGA

The rapid development of Internet technology give people a great number of convenience,Meanwhile it hide a lot of danger.Those danger probably threatens not only people's safety,but also national security.At present,Information security has become a problem that can not be ignored.Cryptography technology is an important guarantee of information security,This technology can effectively prevent information from leakaging and stealing through the encryption transmission of plaintext information,It is the most important and effective means of information protection.Hash algorithm is one of the most important parts of the cryptographic algorithm,Hash algorithm can be apply to digital signature and verifying the signature,so as to ensure the authenticity of the communication status,This algorithm is widely used in various kinds of password system and exchange protocol to ensure the integrity of the information transmissions.At present,Hash algorithm is the most widely used,whose MD5algorithm and SHA-256 algorithm are the most representative because of their high security and wide application.In this thesis,Learning MD5 algorithm and SHA-256 algorithm and proposing architecture optimization scheme are helpful for achieving the hardware implementation and verification.At first,Data path of the algorithm unit is optimized by inserting the intermediate register and preprocessing the input data,The loop iteration operation speed became faster by optimizing the adder design,so as to reduce delay of circuits and shorten the single step critical path.Then this thesis proposed 32 level pipeline design architecture,using 32 level pipeline operating two steps at the same time,This way can enhance algorithm speed,shorten the operation time,improve the data throughput,Data throughput reached 81Gbps.The hardware implementation of SHA-256 algorithm is based on the implementation of MD5 algorithm.Using Quartus II and Questasim software to design and verify simulation,Altera Cyclone-V FPGA is used for hardware implementation verification.The result indicated that the highest clock frequency of the algorithm reaches 173MHz and the data throughput exceeds 81Gbps.Finally,the 0.18?m process is used for MPW tape-out.The chip area is 6mm~2.When the working voltage is 3.3V and the clock frequency is 150MHz,the power consumption is about10.7m W.The results showed that the design achieved the expected functional indicators.