Optimization And Design Of Eaglesong Hash Based On FPGA

With the rapid development of Internet technology and communication methods,modern society has entered the era of big data,people are paying more attention to privacy and information security in the process of information transmission.As a member of modern cipher algorithm,hash algorithm has good security,and can be easily implemented and derived forward.It has played an important role in different fields such as message authentication,electronic payment and blockchain.While the number of Internet users has surged,the amount of data that hash algorithms need to process has skyrocketed,and there is an increasing demand for high-performance hardware implementation of hash functions.Several traditional hash functions have been cracked in recent years,thus,various new hash functions have emerged.Eaglesong algorithm,as one of them,combines simplicity and safety,has a wide application prospect in decryption and blockchain.Based on the above background,this paper proposed an optimized hardware implementation of Eaglesong.The main contents of this paper are as follows:(1)Based on the analysis of the structure of Eaglesong algorithm,the concepts of locality optimization and parallel optimization are adopted in it.Loop fusion technique is used in the process of permutation to improve the instruction level parallelism.As a result,the number of cycles has reduced,the efficiency of Eaglesong algorithm has promoted.(2)A high-performance implementation based on FPGA is proposed for Eaglesong algorithm.This design uses fully-pipeline structure to achieve highest throughput,and registers are inserted into permutation functions for shorter critical path.Through parameter optimization technique,the number of registers in the single round of permutation is reduced,and the pre-calculation technique is applied to simplify the XOR operations and reduce the delay of the logic gate in critical path.The FPGA synthesis and implementation of the design is completed on the Xilinx XC7Z100 platform.The maximum frequency can reach 300.9 MHz,and the throughput can achieve 154.06 Gbps.The throughput of hardware implementation has improved by nearly five orders of magnitude compared with the software implementation.At the same time,the comprehensive results show that after using parameter optimization and pre-calculation technique,the number of registers has decreased by 36.28%.(3)Based on the above Eaglesong module,a simulation digital currency mining system is completed on the Xilinx XC7Z100 platform.The UART bus is used to connect the host computer and FPGA,and the system is tested and verified by serial debugging tool.After comparing the board-level verification results with expected results,the system works perfectly.The results show that hardware implementation of the Eaglesong algorithm can meet the requirements for proof-of-work in the digital currency mining.In summary,this paper has proposed a software optimization of Eaglesong algorithm,and has completed the high-performance hardware implementation of the algorithm.To test and verify the algorithm,a simulation digital currency mining system is built on the FPGA,and the results show that this design can accord with the initial expect.