Design And Implementation Of SHA-3 Algorithms Based On FPGA

Since the 21 st century,information communication has evolved from single point to point communication into global network communication,with the opening of the Internet,the security of information becomes more and more important,security of information has becomes a hot research topic.Cryptography is the cornerstone of information security,and provides security for about 1 trillion global communication equipments,hash function is one of the most important tools in cryptography,which are used for message authentication,electronic signatures and cipher system.Nowadys,with the development of cryptanalysis,the security of hash algorithm has becoming a growing threat.In order to improve the safety of hash algorithm,in 2007 the United States,NIST public campaign SHA-3 algorithm,after five years of screening,Keccak algorithm become the final algorithm.The main work of this paper is focusing on hardware design and implementation of the new SHA-3 algorithm on FPGA,includes following four aspects:(1)Based on the existing research results,this paper makes a deep research on the SHA-3 algorithm,and analyzes the security of the Keccak algorithm from a statistical point of view,and introduces the SHA-3 algorithm applications.(2)According to the properties of the SHA-3 algorithm,we design toplevel circuit architecture of SHA-3 algorithm,and several modules such as control circuit,data read,round function computing,which implements SHA-3 algorithm,data read message filling,process control and data output function.Then we design the hardware of Keccak algorithm,mainly the five-step iteration operation.(3)For different application scenarios,we optimize the hardware design of Keccak algorithm from two dimensions.Firstly,we use speed priority scheme in high speed applications,mainly on the five step iterative algorithm using parallel processing mode.Secondly,in the smart card application environment,we use area priority scheme and the direct memory access method are adopted to run the state machine to achieve the optimization of area.(4)According to the hardware structure design,we verify the functional correctness of algorithm in ModelSim,and implement the hardware based on Kintex7 XC7K410 T FPGA chip.We synthesize the design using ISE14.7.According to the results,in the speed optimization scheme,the highest throughput can reach 9.45 Gbps,and in the area of priority scheme occupied 1350 slice,1204 LUT.In addition,based on the hardware platform of our research group,we gives the application of the SHA-3 algorithm,and put forward a design scheme of encryption card based on FPGA,including the startup process and test scheme.