Design Of Area-efficient Fast Fourier Transform Processor Based On Approximate Computing

With the rapid development of computer science and information technology,Fast Fourier Transform(FFT)is used more widely than before.The research on the throughput and accuracy of FFT processor has entered a relatively mature stage.However,how to reduce the cost of the hardware design of FFT processor is becoming the hot topic in recent years.Approximate computing is an effective way to simplify the hardware logic of fault-tolerant applications.Thus,it becomes an important trend to use approximate computing in the design of low-cost FFT prcocessor,while ensuring the throughput and accuracy.In order to reduce the hardware cost of FFT processor,this paper starts from three aspects of approximate multiplier,twiddle factor accuracy compensation and adder cascade,and proposes a FFT processor design plan based on approximate calculation.In this paper,the common FFT decomposition algorithm and hardware structure are introduced,and the basic FFT processor architecture is determined by comparison and analysis.Reducing the size and number of multipliers in FFT processor can effectively reduce the cost of FFT processor because the multiplier is main part of the cost of hardware in FFT processor.This paper designs the multiplier based on approximate 4-2compression and twice truncation,which can reduce the hardware multiplier cost.For the approximate multiplier,the NLMS algorithm is used to design the twiddle factor compensation mechanism.The storage scheme of the twiddle factor is also optimized.After that,the area and accuracy loss of the FFT processor is reduced.Then,in view of the finite word length effect,a detailed error analysis is carried out for the fixed-point adder in the FFT processor of the convective waterline structure.The software simulation platform is designed and the best adder combination is selected for hardware design.Finally,a low cost FFT processor based on approximate computing is designed.In this paper,a verification scheme of hardware design is developed.The FFT processor design is verified by FPGA.The input is the same random number while output on each stage is compared with the simulation results.After debugging and analysis,the experimental results verify the effectiveness and reliability of the system.The 512 point FFT processor of the 3 level pipelined SDF structure is designed in this paper.The core area of proposed FFT processor is 2.28mm~2 by Design Complier,and the computation accuracy is 53.94dB.Compared with the conventional design,the core area is reduced by 15.24%,with the 1.69dB accuracy loss.