Research And Design Of Key Technology Of High-precision Sigma-delta Analog-to-digital Converter Based On Sensing Application

With the increasing demand for information collection in the fields of industry,biological signals,medical instruments,and home environment monitoring,the performance requirements for related sensors are also getting higher and higher.Based on the requirements of high-resolution scenarios where sensors are mostly in low-frequency bandwidth,Sigma-Delta ADC has become a hot spot in the sensor field at this stage.At the same time,requirements are made for ADC with high accuracy and low power consumption at low speed.With the rapid development of Sigma-Delta ADC over the past decades,various products and papers have emerged one after another,but the way to achieve high precision is nothing more than the modulator order,oversampling rate,and the number of bits of the quantizer.For high-order modulation For devices,the stability of the system loop is still a difficult point in current research.This article focuses on the discrete-time high-precision Sigma-Delta ADC for specific research.Through MATLAB modeling and analysis,a third-order four-bit modulator with128 times oversampling rate is selected to achieve the goal of 18 bit effective number of bits.Utilizing the characteristic of multi-bit quantization that it is not easy to saturate the loop,the NTF function is fitted under 2.6 times the out-of-band gain,which is much larger than the 1.5 times out-of-band gain used in single-bit quantization to achieve a higher signal-to-noise ratio.The non-ideal factors in the actual circuit are analyzed,and the non-ideal factors such as the limited gain and bandwidth of the integrator,clock jitter,charge injection and clock feedthrough are optimized.In the circuit level,a two-stage operational amplifier with high gain and Miller compensation is used to realize an active integrator,and the flicker noise in the integrator is eliminated by adding chopping and adjusting the chopping frequency.The structure of the multi-bit quantizer compares the advantages and disadvantages of Flash and SAR quantization.Because this design belongs to the low-speed field,there is enough time for the SAR quantizer to complete multiple comparisons,and the four-bit quantization only requires 32 unit capacitors.The SAR quantization technology without static power consumption is selected to save power consumption and hardware area.The digital weighted average technology(DWA)is used to calibrate the output result of the quantizer,which reduces the problem of system nonlinearity,increases the signal-to-noise ratio by 3d B,and reduces the impact of Idle tone on the accuracy of the output signal.In this article,the digital filter is designed according to the over-sampling rate of the modulator,and the output signal of the modulator is down-sampled to reduce the signal bandwidth to the range of the signal bandwidth.In this design,the cascade structure is adopted.Through the cascaded comb filter(CIC),compensation filter(CICC)and half-band filter,the high-order number required for a single stage to achieve multiple decimation is reduced,and the hardware is reduced.Area consumption.This design is completed using the 0.18?m process of China Resources Shanghua C1813.The power supply voltage is 1.8V~3.3V,the signal bandwidth is 1KHz,the oversampling rate is 128 times,the modulator structure used is a three-order 4-bit quantized feedforward discrete structure modulator,and the overall power consumption is 290 u W.finally realize19.3bit effective number of modulator.The signal-to-noise ratio reaches 118 d B,the noise floor is 130 d B,the effective number of post-simulations reaches 18.4bit,and the entire chip area is 351?m×641?m(not including digital filter and digital calibration circuit).