Research And Implementation Of The Low Power Applied To The Audio Bandwidth Adjustable Delta-sigma Modulator

Analog-to-digital convertors with high resolution low power become popular in recent years. Since delta-sigma analog-to-digital convertors employs over-sampling and noise-shaping technology, the design requirement of anti-alias filter before analog-to-digital convertors is reduced and noise in signal band is decreased effectively, the SNR of the convertors is improved. Delta-sigma analog-to-digital convertors are widely used in audio application.Based on the demanding of VOIP and different quality hearing aid, this paper designs a delta-sigma modulator with OSR 128,1-V power supply,16 bit, 8KHz/16KHz bandwidth. The modulator is realized by switched-capacitor structure with a single loop forth order CIFF single bit quantization. As the modulator works under two different signal bandwidth models, a MUX control signal is added to control the fourth integrator state to achieve power adjustable in different model. The filter coefficients are firstly gained by using MATLAB SDtoolbox function. Then coefficients are optimized in MATLAB simulink, also non-ideal factors in circuits such as operational amplifier (opamp) finite gain bandwidth, opamp finite DC gain, slew rate, switch on non-linearity and circuits noises are modeled to simulate the effect to the modulator. The circuit blocks such as integrator, sampling switches, comparator, and clock generator are designed. ClassAB amplifier is employed in the modulator to reduce power consumption and increase output slew rate. Bootstrap switches are used to improve the linearity of the sampling switches. Two phase non-overlap clocks used in modulator are generated in the clock generation block. The 128x down-sampling decimation filter has been designed for the modulator. Multi-rate structure cascaded by CIC and CIC compensation and halfband is employed to realize the decimation filter, the filter is implemented by Verilog code.The designed delta-sigma modulator is manufactured in SMIC0.13μm CMOS Mixed Signal process with 153.6μW power consumption, chip core area is 0.98*0.46mm2, and total area with PAD is 1.42*0.87 mm2. The chip SNR reaches 89.3dB and dynamic range reaches to 90.2dB while the modulator works under 16KHz signal bandwidth model, and max SNR is 90.2dB and dynamic range achieves 86dB while the modulator works under 8KHz signal bandwidth model.