Design Of Sigma-Delta Modulator For Linear Isolated System

In many data acquisition and transmission systems,there may be serious interference noise between the signal acquisition end and processing module.For reducing these interference noise,a signal isolator is usually added to " cut off" the direct electrical connection between them.In general,the precision of the isolator is limited.Therefore,to ensure the accuracy,the analog signal need to be digitized before transmission.For this purpose,a medium-speed and high-precision A/D converter is necessary.Due to the inherent anti-aliasing filtering characteristics and the advantage of low power consumption,Continuous-Time Sigma-Delta ADC has become one of the hotspots in the field of medium-speed and high-precision A/D conversion.In this thesis,Continuous-Time Sigma-Delta Modulators with medium bandwidth,high precision and low power consumption are studied,and a third-order feedforward topology with a 4-bit quantizer is designed for the application of linear isolated systems.During the design process,at first,several commonly used loop filter structures are compared,and the feedforward topology is modified to eliminate the additional adder before the quantizer.Moreover,no additional DAC is needed for the modified feedforward topology compared with the hybrid structure.Then,the modulator is modeled based on the Simulink tool.From the perspectives of theory and model simulation,various nonidealities of the modulator are analyzed,and the performance requirements of the circuits are determined.Finally,each sub-module of the modulator is designed according to the simulation results,including a third order loop filter,a 4-bit quantizer and feedback DAC with nonlinear error correction circuits based on data-weighted-averaging(DWA)algorithm.The operational amplifier in the loop filter adopts the two-stage architecture with class AB output for higher slew rate.Compared with the traditional flash structure,a 4-bit SAR-based quantizer is used to achieve lower power consumption and smaller area.And for high speed and accuracy considerations,a current-steer based feedback DAC is implemented.In addition,the nonlinear error correction circuit using the first-order DWA algorithm is also designed to reduce the requirement of DAC mismatch.Considering that the SAR quantizer will introduce a large amount of latency,which may lead to potential instabilities,a zero-order feedback path is added to compensate the excessloop delay caused by the quantizer.In the design of the compensation circuit,it is found that the traditional compensation method based on the current-steer feedback DAC will introduce additional poles and make the loop unstable.Therefore,a new delay compensation method based on a switched capacitor(SC)DAC is proposed and designed.Simulation results show that the new method can achieve higher stability and accuracy with lower power consumption compared with the traditional one.The third-order Continuous-Time Sigma-Delta Modulator with a 4-bit quantizer is implemented and simulated in TSMC 0.18?m CMOS technology.Sampling at 64 MHz and with the DAC mismatch of%,simulation results show that the modulator achieves 83.6 dB SNDR and 13.6 bits ENOB within 1.333 MHz bandwidth.The modulator dissipates 2.587 mW at 1.8 V supply voltage,and the Walden figure of merit is only 78.4 fJ/conv-step,which meets the requirements preset before.