Research And Design Of Delta-Sigma ADC With High Precision And Low Power Consumption

In recent years,due to the rapid development of digital signal processing(DSP)technologies,many computing and signal processing tasks are mainly realized by digital means.Every year,the speed and density of digital integrated circuits are increasing,which consolidates the dominant position of digital circuits in the field of communications and consumer products.But the physical world is still the world of analog signals,so the analog-to-digital converter(ADC)is needed as the interface between the physical world and the digital world.With the improvement of speed and performance of DSP,the speed and accuracy of ADC associated with this need to be further improved.Delta-Sigma ADC uses over-sampling and noise-shaping technology to achieve high accuracy that traditional ADC can not achieve.Delta-Sigma ADC has been widely used in various fields such as industrial measurement,digital audio and communication.Delta-Sigma ADC is composed of Delta-Sigma modulator and digital decimation filter.In order to effectively improve the overall performance of the modulator,this design adopts a single-loop,fifth-order,tri-level analog modulator with feedforward path.The main advantage of 1.5-bit quantizer is that it can reduce the output swing of integrator,thus reducing the requirement of analog circuit design.Two negative feedback loops are used in the modulator to minimize quantization noise in the signal band and push most of the noise to high frequency.Combining with the design flow of the modulator in this paper,firstly,using the SDToolbox in Matlab,the behavior level modeling and simulation of the modulator system are completed.Then,in order to further confirm the stability of the modulator system,Verilog-A model is used to verify the performance of the system in Cadence.For transistor-level circuit design,Delta-Sigma modulator adopts fully differential switched capacitor circuit,which effectively reduces harmonics,power consumption and the influence of circuit nonlinearity.The proposed Delta-Sigma ADC achieves a signal-to-noise-and-distortion ratio(SNDR)of 100 dB with an oversampling ratio of256.The active die area of the ADC is 2 mm~2 in a 0.35?m CMOS process.Total power consumption is less than 3.7 mW.The expected design target of the modulator is realized,and the requirement of high precision is achieved.Finally,the layout of the whole chip has been drawn.