Research And Design Of High-precision 12-bit SAR ADC

Today's world is already a digital world.People's lives have been profoundly changed by technology.Portable electronic products such as mobile phones,computers and smart home devices are widely used.Connecting digital systems with the real world is the first step in entering a new era.The digital converter has assumed this important role.Therefore,designing ADC circuits suitable for different application scenarios has become a major focus in analog circuit design.After decades of continuous development,ADC circuits have derived many circuit structures such as Flash ADCs,pipeline ADCs,Sigma-Delta ADCs,and SAR ADCs.Among them,the SAR ADC has low power consumption and high accuracy.Compared with other ADC circuits,the same power consumption can achieve higher accuracy.At the same time,SAR ADCs generally also have a smaller chip area.These advantages make the SAR ADC can adapt to the constantly updated application environment,so it has been widely used in systems such as touch screens,biomedical,sensors,and wireless networks.The feature size of the integrated circuit silicon gate has also been reduced to the nanometer level,and a highly integrated,cost-effective system-on-chip has also emerged.Therefore,the design and implementation of nanometer CMOS SAR A/D converters have attracted more and more IC designers' attention.After studying and analyzing the algorithms,circuit structure,and circuit characteristics of mainstream analog-to-digital converter circuits on the market,this paper proposes a highprecision 12-bit ADC based on successive approximation.The SAR ADC compares the input voltage with the voltage generated by the DAC module in the circuit,thereby continuously narrowing the search range to determine the digital output code.The comparison result of the comparator during the conversion is input to the SAR control logic,and the input when the DAC generates the comparison voltage during the next comparison is obtained.Among them,the comparison latch circuit adopts a high-speed comparator structure with an added preamplifier,and combines the negative exponential response of the amplifier with the positive exponential response of the latch to improve the speed of the comparator.At the same time,a combining input and output offset correction circuit is added to improve the accuracy of the comparator.The DAC module uses a segmented DAC to reduce the size of the components used in the DAC.The high-position DAC uses a charge storage type and uses a thermometer code for control to improve the static and dynamic characteristics of the DAC module.The low-position DAC uses a resistance tree structure to ensure low positions DAC conversion is monotonic.The high-position DAC combines the sample-and-hold circuit with the DAC circuit,saving the overall chip area.A bias module is added to the ADC chip to reduce the sensitivity of the overall circuit to changes in external conditions.The bias current in the bias module is the zero temperature coefficient current calculated by the positive and negative temperature coefficient currents.After the circuit design is completed,the layout of the circuit module is also discussed in detail in this article.After simulation test,this article has obtained a 12 bits successive approximation ADC circuit with a sampling rate of 265KS/sunder the GSMC 0.18,?m process,a nd the circuit is tested at the Nyquist frequency,SNR is 73.65dB,SFDR is 90dB,the effective number of bits is 11.91,and the power consumption is 8.25?W,FO M is 4.2 fJ/conv-step.