Research And Implementation Of Low Voltage SRAM Built-in Self Test Circuit Technology

As the manufacturing process of integrated circuits continues to advance,fault models and test methods for low-voltage SRAMs are receiving more attention and research.In recent years,test methods for low-voltage SRAMs have been endless.For SRAM testing,people prefer to use the MBIST(Memory Built-in Self Test)method for testing,because this method is not limited by the number of chip pins and the tester's memory capacity,reducing the memory test's dependence on ATE(Automatic Test Machine).Moreover,using the BIST approach can shorten the test cycle of the chip,advance the time to market,simplify the generation of test vectors and support multiple test algorithms,and reduce the space and cost of storing test vectors.The main work of this paper includes:(1)Based on the background and development status of lowvoltage SRAM testing,summed up and compared the fault types and test methods in low-voltage SRAM,and designed a special DFT for the stability fault in low-voltage SRAM.The circuit is used to detect stability faults.(2)Based on the March C+ algorithm,this paper deduces the corresponding detection algorithm based on fault primitives to detect more types of faults and improves the fault coverage of the algorithm.(3)Finally verify the validity of the DFT circuit and the built-in self-test circuit by simulation respectively,compare the new March-Like algorithm with the March C+ algorithm,and verify the effectiveness of the new algorithm.This paper mainly studies the fault model and test algorithm of low-voltage SRAM.Based on SMIC 40 nm LL CMOS process,a 256 Kbits low-voltage 8T SRAM chip is designed for testability and the tape is completed.Simulation and experimental results show that the DFT circuit designed in this paper can reduce the minimum detectable resistance of the stability fault from 1G to several hundred megahertz and improve the test sensitivity.;the new March algorithm proposed in this paper can effectively detect the coupling of write failure,write interference failure and read disturbance failure in the low voltage SRAM array,The coverage rate reaches 100%.Built-in Self Test circuit will increase the area overhead of the chip to a certain extent,but it can improve the fault coverage of the algorithm as a whole,and works well.