Font Size: a A A

Research And Design Of Low-Voltage SRAM Circuit For Error-Tolerated Applications

Posted on:2022-12-18Degree:MasterType:Thesis
Country:ChinaCandidate:M H HuangFull Text:PDF
GTID:2518306764973049Subject:Computer Hardware Technology
Abstract/Summary:PDF Full Text Request
With the development of portable mobile devices and high-speed networks,the demand for low-power design is increasing.As an important part of System on Chip(So C),Static Random Access Memory(SRAM)is widely used in computers and mobile devices.Therefore,the low power design of SRAM can effectively reduce system power consumption.Reducing voltage is an effective low-power design method,but with the decrease of voltage,the performance of SRAM is affected.Especially under ultra-low voltage,the traditional 6T SRAM circuit can not work properly.Therefore,it needs to design special SRAM bit cells for ultra-low voltage.In addition to voltage reduction,approximate design is also an effective low power design method for error-tolerant applications.Based on the designed SRAM bitb cell,combined with the proposed approximate SRAM circuit architecture,the power consumption of SRAM circuit can be further reduced.First,this thesis gives an overview of low voltage SRAM design and approximate SRAM design.Then on the basis of summarizing the existing work,we propose a SRAM bit cell with high performance under low voltage,and introduce the working mode of the bit cell in detail.Then the parameters of the cell circuit are simulated.At 0.5V supply voltage,TT corner and 25?,Read Static Noise Margin(RSNM)and Write Margin(WM)of proposed bit cell are 21.6 times and 5.82 times that of the conventional 6T bit cell,respectively.An error tolerant application oriented approximate SRAM architecture is proposed,and the proposed bit cell is applied to the approximate SRAM architecture as the storage units.Combined with the corresponding peripheral circuits and assistant technologies,a 16 kb SRAM circuit is designed.Finally,simulation and functional analysis of the SRAM circuit are carried out in a 40-nm standard CMOS technology.The results show that the proposed approximate SRAM circuit has an operating frequency of267 MHz and an average power consumption of 4.4?W at 0.5V supply voltage,TT corner and 25?.
Keywords/Search Tags:SRAM, Low Voltage, Low Power, Approximation Design
PDF Full Text Request
Related items