Design And Implementation Of NVM Over Ethernet Storage Protocol And Device For TTE Switch

TTE,Time-Triggered Ethernet,is a kind of real-time deterministic Ethernet which can be applied in the field of rail transit and high-level industrial control.It has the communication ability of real-time determination and security fault tolerance.To enhance the reliability and error traceability of the network system using TTE,the TT service data can be backed up to a mass storage device.NAND Flash,as a kind of Non-Volatile Memory(NVM),is widely used in the field of solid-state storage due to its advantages of easy integration of large capacity,shock resistance,impact resistance and low cost.The control of NAND Flash usually requires the help of CPU.However,it is difficult to provide additional CPU resources to control NAND Flash in some resource-constrained systems that use TTE switches in special scenarios.Also,the pure hardware control without CPU can improve the reliability of storage control.Therefore,it is necessary to design a set of NAND Flash control system which does not need local CPU control and can be easily integrated with Time-Triggered Ethernet switch.It needs to carry the storage operation in the Ethernet data communication according to the custom protocol.Firstly,this dissertation introduces the two kinds of storage protocol and architectures,which are commonly used in the field of large capacity solid state storage: NVMe protocol and Open Channel storage architecture,and their command set,SQ/CQ queue characteristics and operation flow are briefly described.A hardware architecture of Open Channel SSD developed by ourselves is also been given.Then combining the previous two storage architectures,the NVM over Ethernet storage protocol and architecture designed in this dissertation r is proposed,and the definition of command set and operation flow are explained.Secondly,considering the adaption of Ethernet interface of TTE switch,a scheme of NVM over Ethernet storage controller which is suitable to be combined with switch and uses Ethernet interface as front end is given.Thirdly,the module level design of the key modules in the storage controller and the working principle of its internal important mechanism are described in detail.Fourthly,Cadence NCSIM and Sim Vision are used to simulate and analyze the design.It is proved that the NVM over Ethernet storage system proposed in this dissertation can successfully carry out various storage command operations on NAND Flash without the participation of local CPU and can be conveniently integrated with the switch through the Ethernet interface.Finally,the controller is tested on FPGA board to verify the correctness of its operation on NAND Flash chip.The innovation points of this dissertation include: Firstly,a storage controller with Ethernet interface is designed,which is easy to be integrated with the switch.It solves the problem that it is difficult for the switch and the storage device to work together for data backup.Secondly,the NVMo E storage architecture in this dissertation does not require local CPU to participate in the work,which greatly reduces the hardware board level resource overhead,and pure hardware protocol analysis can not only improve performance,but also improve reliability.Thirdly,four NAND Flash targets can be operated simultaneously in a single NAND Flash channel,which will greatly increase theoretical throughput and solve the rate reduction problem caused by the use of NAND Flash asynchronous interface.Finally,the strategy of writing and reading data from NAND Flash allows for one-to-one matching of Page data to NAND Flash pages as needed,improving NAND Flash capacity utilization,and avoiding error spread in the event of read and write errors.