Research On Key Technologies Of NAND Flash Solid State Storage Reliability

NAND Flash memory is replacing magnetic disks because of its fast random access performance,shock resistance,and low power consumption.Its capacity has continuously increased and cost has continuously decreased over decades.This positive growth is a result of two key trends:(1)effective process technology scaling;and(2)multi-level(e.g.,MLC,TLC)cell data coding.However,this also resulted in reduced reliability of NAND Flash data storage.ECC(Error Correcting Code)has limited error correction capability.Therefore,NAND F lash's reliability-related memory characteristics are studied.It is meaningful to explore optimization strategies that improve storage reliability based on these characteristics.The reliability of the NAND Flash chip is closely related to Program and Era se cycles(P/E),bit error rate(BER),and programming latency.These parameter values need to be obtained on the actual chip test,so we have developed a NAND Flash test platform based on Zynq 7000 series all-programmable logic device as the main controller,using Xilinx new development tool Vivado.The platform can implement basic operations such as program,erase and read on NAND Flash chips and can adapt to NAND Flash chips with different page sizes.In this paper,the NAND Flash chip is tested on this platform to obtain real data.The following studies have been made.(1)This work designed experiments to explore the relationship between the NAND Flash P/E cycles,BER and programming latency,a model for evaluating chip reliability using programming latency was established.In this paper,the programming latency is used to replace the P/E cycle number as an indicator of the NAND Flash wear level,that is,reliability.A wear-leveling strategy based on programming latency is proposed.(2)This work designed experiments to vertify the existence of the self-recovery effect of NAND Flash.We have explored the change rule of data retention error under different degrees of self-recovery effect for blocks with different write/erase stresses.According to the rule,a wear-leveling strategy focusing on self-recovery effect is proposed.The core idea of this strategy is when the chip performs wear leveling operations,among the blocks with the same number of P/E cycles,the block with the earliest program time is preferentially selected for programing.Using this strategy can extend the retention time of the data.