| Owing to NAND flash memory offers several following advantages of non-volatility,fast access speed, large storage capacity, low power consumption and resistance to shocks, it has been widely adopted in kinds of measurement systems which have the measure requirements of large storage capacity and high sampling frequency. To realize higher storage capacity and lower 1-bit storage costs, NAND flash is continuously scaled down with the development of semiconductor manufacturing process. However, the decreasing of gap between two adjacent threshold voltages in each memory cell causes the increasing bit error rate(BER) of NAND flash. Because the flash memory cell can only afford a limited Program/Erase(P/E) cycles, the lifetime of NAND flash is also very limited.Therefore, there would be extremely significant to study the relevant management strategies to reduce the BER and extend the lifetime of NAND flash.Based on the characteristics of NAND flash memory, this dissertation provides the following four management strategies for NAND flash storage system: the preprocessing of programmed data, an optimization algorithm of flash translation layer(FTL), the prediction model of the average BER, and an achievable page-granularity wear-leveling strategy. In addition, all these strategies are verified in a real experimental platform of NAND flash.The main contents and research contributions of this dissertation are as follows:1. To reduce the primary BER of NAND flash, this dissertation firstly discusses the strong correlation between data pattern and program-disturb and data retention errors, and then presents a joint coding strategy based on data pattern variance. The key of this strategy is to increase the ratio ’1’s in the programming data using a Nibble Remapping Coding(NRC). Besides, aided with the shorted BCH code, the joint coding strategy can realize the data protection during the process of NRC encoding and NRC decoding. Because the joint coding strategy does not change the length of data during encoding and decoding process, it does not consume any extra user data area of NAND flash. Therefore, it can be transparently fit within the FTL algorithms. The experimental results show the presented joint coding strategy reduces the program disturb BER by 90% and the data retention BER by 98%, while experiencing a slight access speed degradation.2. To extend the lifetime of NAND flash, this dissertation firstly investigates the distinct variances of BER in different pages, and then presents a novel page endurance variance aware(PEVA) strategy. The PEVA strategy fuses and optimizes the principle of traditional FTL address mapping and bad block management(BBM). Specifically, PEVA translates the coarse-grained BBM of the low-level driver layer into fine-grained bad page management in the FTL to exploit the lifetime potency of every page in a block. The experimental results show that PEVA without extra hardware overhead can extend the lifetime of NAND flash by at most 9.8× compared with the conventional BBM.3. This dissertation provides a detailed analysis of the characteristics of retention error with retention time and P/E cycles, and then presents an average page raw BER prediction model based on a polynomial function. Rely on this prediction model and the endurance variance in NAND flash page, this dissertation further presents a fine-grained and achievable page-granularity wear-leveling(PGWL) strategy. PGWL can evaluate the BER level of data page using the BER prediction model to dynamically operate the program relief in real time. The experimental results show that PGWL can extend the lifetime of NAND flash by approximately 87.8% compared with the conventional blockgranularity wear-leveling strategy, while the overhead of data throughout caused by PGWL can be ignored.
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