Research And Implementation Of Parallel Storage System Based On NAND Flash

With the high development of the Imformation technology, the demand for datastorage capacity and speed is growing. The mechanical HDD adopted by traditionalcomputer storage system has become the bottlenecks of storage system and can’tmeet the demand of the future appications because of its huge I/O access latency,high power cusumption and poor shock resistance. At the same time, afterprogressive development of a number of technical change, the NAND Flash-basedsoild state storage system which has rapid read and write speed, non-volatile, goodshock resistance and low power consumption gradually revealings its great advantageand attracts the attention of the domestic and foreign scholars and the industry. Itmay replace the traditional HDD in the future. However, the issue of increasing theactual Flash access bandwidth, decreasing the I/O latency and exploting theparallisms between multi-channels should be considered in the design of solid statestorage system.This paper designs and implements a multi-ways storage systems based onNAND Flash. Through using FPGA as the developemt platform and exploting theSOPC technology, the design constructs a solid state storage controller architecturein the FPGA. By exploting serval high capacity Intel NAND Flash chips, it constructsa multi-ways parallel solid state storage system. The system is connected to the hostby SATA and uses serval independent NAND Flash controllers to increase the accessbandwidth of NAND Flash by explot parallel bus broaden technology. This paperdoes a research for the FTL of the multi-channel architecture. Firstly, it proposes ahybrid address translation scheme which is based on super block and μ-tree. On theone hand, this address translation scheme can explot the multi parallisms of themulti-channel architecture. On the other hand, it reduces the RAM memoryconsumption of address translation. Secondly, in order to explot the advantage ofCopy-back command in the advanced NAND Flash and shorten the garbage collectiontime, the FTL optimizes the traditional greedy algorithm and proposes a newdefinition of dirty block. Thirdly, the FTL proposes a wear-leveling algorithm basedhot and cold data indentification to optimize the disadvantage of the traditionaldynamic garbage collection algorithm. At the end of this paper, the module andsystem is tested and validated. It presents the test platform, method and processes, then gets the test results and draws the validated conclusions. The tese results showsthat this parallel solid state storage system can word stablely and has good prallellsim.