The FPGA Implementation Of Low-Density Parity-Check Codes

Low-Density Parity-Check (LDPC) codes are a class of capacity approaching error-correcting codes. For long code lengths, LDPC codes can even outperform Turbo codes. Due to the advantages of lower complexity of decoding,lower error floor and the changeable code rate and length,LDPC codes have become the serious competitors to Turbo codes.At present , LDPC codes have been widely used in the area of deep-space communication,fiber communication,the digital video and audio broadcast of satellite communications etc.Hence, the study on the hardware implementation of LDPC codes has become one of the most attractive issues in channel coding community.This thesis analyzes the basic encoding schemes.Firstly, we introduce the random construction methods of LDPC codes, including the progressive-edge-growth (PEG) algorithm.And than we study the construction of Quasi-cyclic (QC) LDPC codes using the cycle elimination (CE) algorithm.Secondly, we compare three decoding methods and discuss the Turbo-Decoding Message-Passing (TDMP) algorithm which can be easily implemented in hardware. We simulate TDMP algorithm and find it has great performance advantage. Finally,an (4096,2048) TDMP decoder is desigened based on Altera Stratix EP1S25 FPGA device which using four single parity check units to decode one frame in parallel and three frames are decoded simultaneously. This thesis analyzes the structure of the decoder and its working flow.