| Low density parity-check (LDPC) code was proposed in 1962 by Gallager, which is one kind of the near Shannon Limitation error correction code. Many telecommunication organizations and companies will have LDPC to be the Error-Correcting scheme of the fourth generation mobile communications standard. Recently, LDPC code has drawn the worldwide attentions in channel coding community. This paper performs deep studies on the theory and hardware implementation of LDPC codes respectively, and finally completes the hardware design of its encoder and decoder structure.With regard to the theory research, firstly, basic theory and structure method of LDPC codes are studied. Then, the traditional encoding algorithms, effective coding based on approximate lower triangle matrix and quasi-regular LDPC encoding algorithm based on Q matrix are analyzed in detail. We study three decoding algorithms: hard-decision decoding algorithm, BP decoding algorithm and BP_based decoding algorithm. The analytical result show the BP_based algorithm is suitable for the hardware implementation.With regard to the hardware implementation, firstly, the LDPC codes are constructed using the Matlab programming. Then, computer simulation is performed on its encoding and decoding. Finally, hardware design of one kind of universal encoder whose rate is 0.5 and parallel decoder based on BP_based decoding algorithm are accomplished on the QUARTUS II software platform by the Verilog HDL language. The whole design is validated on the circuit using SignalTap II. |
