Research On3D IC Automatic Placement

With the scale of the integrated circuit interconnects increases, growth, lead toincreased latency interconnect, and impact circuit performance and development,reduce the interconnect length of integrated circuit becomes the key to thedevelopment of integrated circuits.3D integrated circuit technology is a newtechnology of multilayer chip stacked, multilayer chip between the through hole----TSV interconnect through key silicon, interconnect length can effectively reducethe circuit, improve circuit performance, is the hotspot with the development of theintegrated circuit. To advance the development of3D integrated circuit technology,the related research at home and abroad carried out a large number of3D integratedcircuit automatic design.Research of3D integrated circuit automatic layout, more concentratedmanufacturing method and TSV materials used in TSV field, EDA field about TSVis less. Among them, through the TSV layout technique to reduce interconnect lengthis very important, the scanty3D chip performance improvement. Therefore, thispaper aimed at the problem, research.The TSV point positioning method, TSV location method and TSV griddingmethod, in order to reduce the3D integrated circuit interconnect length, improve theautomatic layout, optimization of circuit performance;The TSV spacing adjustmentmethod, anti crosstalk TSV adjustment method and TSV thermal adjustment method,to solve the spacing of TSV violation process constraint, TSV high frequency ofcrosstalk and3D integrated circuit heat problem.TSV automatic layout based on the method presented in this paper, theformation of3D integrated circuit automatic layout system. This software is basedon Linux operating system, through the script language structures. The test circuit ofIBM company3D integrated circuit automatic layout verification, including the TSVpositioning and TSV adjustment. Finally the layout result and interconnect lengthstatistics.3D integrated circuit TSV automatic layout results interconnect length statistics,TSV regional positioning results than has been reported for layout optimization ofcircuit interconnect length reaches up to11.82%, TSV midpoint location comparedregional results method has lower, than has been reported for layout optimizationresults up to9.12%, but the layout of the speed ratio method the reported increased7.79times, TSV anti crosstalk adjusted interconnect2.81%at the expense of the circuit, TSV cooling adjusted sacrifice circuit interconnect circuit1.18%, peaktemperature decreased5.69K after adjustment.