Timing Optimization Design Of Large-Capacity On-Chip Memory And Memory Interface Based On 28nm CMOS Technology

This paper is based on 28 nm standard CMOS?Complementary Metal Oxide Semiconductor?technology of three components of an MX chip.It mainly study that timing optimization of three key modules of shared memory module,external memory interface module and DDR3?Double Data Rate 3 SDRAM?storage interface.The main methods include:Since the memory capacity of the shared memory module is large,routing congestion occurs and there are various timing issues.The shared memory module has a total capacity of 4MB,and it works at 500 MHz,and the bus is 128 bits wide.By optimizing the floorplan,it can reduce the difficulty of timing optimization.In this paper,manual planning is adopted to optimize the location of macro units and the timing-related register locations.By adjusting the location and direction of the macro unit,the average area of a Bank Memory is reduced by 6%,which avoids the routing congestion and reduces the difficulty of routing.By optimizing the location of register,the delay of reg2 reg data path is reduced.In this paper,by manually planning the clock tree,the time delay from the clock root to the memory body is reduced by an average of 2.4%,and the clock skew is reduced by 32 ps.By manually adjusting the clock tree routing method,the antiinterference ability of clock tree trunk was increased,and the clock crosstalk of the memory body was reduced by 49 ps.For timing paths which related to memory,in addition to the usual timing optimization methods,such as clock skew and substitution threshold,this paper aims to optimize the output circuit logic structure of the memory Banks and reduces the average delay of the storage body to the next level register by 54.7 percent.By manually planning the register output to the specific path of the storage body LS terminal,reducing the use of the long interconnection line,the delay of the data path is reduced by an average of 22.1%.By optimizing the clock tree structure and the timing path related to memory,the problem of routing congestion of the L3 parts is finally solved,and the timing convergence of the module is realized.Because there are two asynchronous clocks inside the external storage interface module,and the module is interacting with the top,it has a large number of timing violations of the internal cross-clock path and the interface interacting with the top-level.The width of the module bus is 32 bits.It contains two asynchronous clocks,ECLKOUT clock and CLK clock,and the clock frequency is 100 MHz and 500 MHz respectively.For the timing problem of interface,the addition of buffer at the interface by the TCL script removes1243 hold time violation of function mode ML_rcworst₁25C corner.According to the hold violation of the internal cross clock domain of EMIF,the method of replacing the threshold value with ice and Prime Time tools was used to finally fix the 3870 violations under the worst corner.Because of the requirement of skew between the internal PHY and IO of DDR3,the timing closure within DDR3 is the focus of research.The DDR3 is based on the 28 nm CMOS technology,which supports the addition of 8GB of storage capacity,and the transmission rate is 1600 Mbps.By manually planning the clock tree to the PHY,it can basically balance the clock of PHY,and also reduce the difficulty of balancing the delay between the PHY and IO.The corresponding algorithm is designed to realize equal-spacing and the same levels insertion of buffers between data PHY and IO instantly.On this basis,using Innovus tool complete routing,the skew between the data PHY and the corresponding IO meets the design requirements.