Research On Structure Optimization And Process Fluctuation Of Junctionless FET

With the scaling of semiconductor devices under the guidance of Moore’s Law,traditional transistors represented by MOSFETs are facing serious process and performance challenges.MOSFET based on drift-diffusion mechanism can not reach a sub-threshold swing below 60 m V/dec,which limits the switching speed,and power dissipation of device.Hence,junctionless(JL)transistors with uniform doping of the whole device;stacked channel(NS: Nanosheet)transistors,and tunneling field effect transistors(TFET)based on tunneling mechanism have been extensively studied.Meanwhile,the influence of random process fluctuations in nano-scale devices is increasing,which seriously affects the performance and reliability of the devices.Research on random process fluctuations in nano-scale devices has also attracted much attention.Compared with traditional MOSFET,JL transistor avoids the ultra-steep pn junction,which reduces the thermal budget,and provides a strong impetus for device scaling.NSFET devices are greatly integrated into FinFET process flow and the vertical placement of multiple channels is realized by the use of suspension etching.Its stronger gate con trol ability effectively suppresses the short channel effect.In addition,TFET device that based on band-to-band tunneling mechanism enables carriers to tunnel between the conduction band and valence band of the channel/source region through quantum effec ts,TFET achieves a lower subthreshold swing,which makes it attract attention.However,the low doping concentration of source and drain in JL FET brings about a large resistance,and the relatively high doping concentration in channel region makes the influence of the random doping distribution more serious.The complex structure of NSFET makes it subject to more structural changes and process fluctuations.TFET devices are subject to lower on-state currents and severe bipolar effects.At the same time,t he influence of gate metal work function fluctuation(WFV),random dopant fluctuation(RDF)and line edge roughness(LER)can no t be ignored.This makes it necessary to consider the impact of process fluctuations in the research of new device s.The work of this thesis is mainly divided into the following three parts:1)Compare the difference of process fluctuations in NSFET under inversion(IM: Inversion Mode),junctionless(JL: Junctionless Mode)and junctionless accumulation mode(JLAM: Junctionless Accumulation Mode).It is found that JLAM device achieves similar transfer characteristics as the IM device on the basis of th e simple process.However,it is also affected by severe LER and WFV,and the overall process fluctuations in JLAM have the greatest impact.2)Analyze the influence of NSFET device structure on process fluctuations.Through TCAD simulation,it is found t hat RDF is most sensitive to the doping concentration in channel.The doping concentration of the channel region can be reduced to alleviate the influence of RDF.WFV is different from the grain size and crystal orientation of metal gate materials,and it is greatly affected by the physical thickness of gate oxide.The effect of WFV can be alleviated by using a thicker oxide layer;while LER is related to the device doping concentration,and other structural parameters have less impact on LER.3)A new typ e of HGD-DMG-CJTFET device based on heterogeneous gate dielectric(HGD)and dual metal gate electrode(DMG)structure is proposed to alleviate the low on-state current and severe bipolar effect in TFET.HGD structure suppresses the influence of gate edge e lectric field by adopting a low-k oxide layer on the source region,and it can realize a 200-fold improvement in on-state current.In the DMG structure,a metal electrode with a specific work function is used at the channel/drain region interface to realize the modulation of the carriers and energy bands in the semiconductor,which achieves a wider tunneling distance at the reverse tunneling interface,and suppresses the bipolar current effectively.