Modeling And Simulation Of Tunneling Transistors, And Nanowire Transistors

The scaling of conventional planar Si MOSFET is approaching its physical limit. Among many possible successors, tunneling FET (TFET) and nanowire FET (NWFET) are becoming the most promising candidates, due to their excellent theoretical device performance and achievable fabrication process. Parts of the physical characteristics of these two devices are studied in this thesis.In the first chapter, the background and significance of this work are briefly presented. In the beginning of the second chapter, we briefly introduce the fundamental properties of NWFET. Then we establish the 2D gate tunneling model in the cylindrical gate NWFET. Under the assumption of the same device performance, by comparing with the gate tunneling characteristics of planar gate FET, we get the conclusions that the gate tunneling current for NWFET is reduced and the reduction is related to the oxide thickness and the radius of NW. Based on that, a quantum correction is further considered, including the rise of ground state level, the split of energy valley degeneracy induced by anisotropic effective mass, and then the valley competition effect is predicted. Next we apply the tunneling model with quantum correction to investigate the leakage characteristics of NWFET with Si, Ge, and III-V alloy as channel material. The third chapter begins with an introduction of basic properties of TFET and the band-to-band tunneling model used in our simulation. Then the characteristics change by inserting a thin N-type layer into the traditional P-I-N structure is discussed. By using theoretical simulation, we conclude that the TFET with P-N-I-N structure not only improve the sub-threshold swing (SS) and the turn-on current, but also the reliability of TFET.