Study Of The Structure Optimization Of The Heterojunction Tunneling-field Effect Transistors

With the development of microelectronic integrated circuit technology,the feature size of MOSFET is reduced proportionally,and the circuit integration is continuously improved.However,as the size of transistors shrinks,the short-channel effect and quantum effect have become increasingly serious.In addition,because the MOSFET cannot have a subthreshold swing?SS?below 60 mV/decade at room temperature,the off-state current increases with the subthreshold voltage decreases,which results an increase in the device power consumption.These problems make traditional CMOS technology difficult to meet the requirements of integrated circuit low-power design.To continue the”Moore”law and solve the power consumption problem of integrated circuits,the most effective way is to develop new ultra-low power devices that can replace MOSFET.In these new ultra-low power devices,the tunnel field-effect transistor?TFET?based on the band-to-band tunneling can achieve a sub-60 mV/decade subthreshold swing at room temperature.TFET not only can effectively reduce device power consumption at a small operating voltage due to the lower off-state current,but also is compatible with CMOS process technology.Therefore,TFET is one of the most promising micro-nano low-power devices.The conventional silicon-based TFET devices are faced with problems such as low on-state current,poor radio frequency characteristics and ambipolar behavior,which severely limit the wide application of TFETs in practical circuits.Therefore,to improve the performance of TFET including increasing the on-state current,effectively suppressing the ambipolar effect and improving the RF characteristics,this paper mainly optimizes the traditional TFET from both structural engineering and materials engineering.The main research work of this paper can be summarized as the following three parts.1)A Ge/Si heterojunction L-shaped tunnel field-effect transistor combined with hetero-gate-dielectric?GHL-TFET?is proposed.GHL-TFET has a Ge-source with small band gap and forms a Ge/Si heterostructure at the interface between the source and channel with a smal-l tunneling barrier,which can increase the carrier tunneling rate and significantly improve on-state current.What is more,benefiting from the hetero-gate-dielectric?HGD?structure,GHL-TFET can increase the reverse tunneling barrier width by reducing the gate control over the drain/channel interface to effectively suppress the ambipolar current.Simulation results indicate that GHL-TFET exhibits larger on-state current,better suppression of am-bipolar effect,and better analog/RF performance compared with conventional L-TFET.2)A GaAs_0.5Sb_0.5/In_0.53Ga_0.47As heterojunction Z-gate tunnel FET combined with hetero-gate-dielectric?HGD-HZ-TFET?is proposed.By using the GaAs_0.5Sb_0.5/In_0.53Ga_0.47As het-erojunction structure with direct bandgap III-V compounds,HGD-HZ-TFET has a steeper tunneling junction,which reduces the carrier tunneling barrier height and width and great-ly improves the on-state current.And the application of the hetero-gate-dielectric structure effectively suppresses the bipolar effect.In addition,analog/RF performance of HGD-HZ-TFET are also improved in terms of higher transconductance,cut-off frequency and gain bandwidth product,and lower parasitic capacitance.Then,to optimize device performance for HGD-HZ-TFET,the following conclusions are obtained.First,when the left boundary of the gate overlap channel region is aligned with source/channel interface,HGD-HZ-TFET exhibits higher on-state current.Then,although reducing Sb and increasing Ga is an effec-tive way to improve on-current,it is also accompanied by large off-current at the same time,which increases the power consumption of the HGD-HZ-TFET.3)Combined with the CMOS process technology,the process flows of the proposed GHL-TFET and HGD-HZ-TFET are introduced,which to lay a theoretical foundation for future process realization.