Key Technologies For Si-based Strained Junctionless Tunneling Field Effect Transistor

With the improvement of integrated circuit manufacturing technology and the reduction of feature size to nanometer level,the development of Moore's law has entered a bottleneck stage.In order to continue to push forward Moore's law and enhance the integration and performance of integrated circuits,researchers turned their attention to TFET?tunnel field effect transistor?.TFET has obvious advantages over MOSFET?metal oxide semiconductor field effect transistor?in terms of static power consumption and switching speed,so TFET is the optional device structure for ultra-low power chip.In this paper,the effects of materials,heterojunctions and strains on the electrical properties of Si-based junctionless TFET devices are studied,which provides a technical reference for the application of high performance TFET in semiconductor field.Based on the working mechanism of the tunneling field effect transistor,the influence of structural parameters,material characteristics,heterojunction and strain on the electrical characteristics of Si based junctionless TFET devices is analyzed in detail by using Sentaurus TCAD simulation software.The results show that the Si junction type double gate n-TFET is larger than the conventional PIN TFET,and the structure is all n type heavy doping.The on/off current ratio of the device increases to 7.7×10⁵.By optimizing the gate oxide thickness and gate metal work function and other physical parameters,the device performance can be further improved.The electrical properties of the junction devices are significantly related to device materials.Using Ge as the device material can increases the tunneling probability in on state to increase the on-state current to 1.2×10^-6A/?m.Then,based on the characteristics of Si and Ge materials,a Si_1-xGe_x double-gate junctionless TFET structure is designed.The electrical characteristics of the device are compared with those of different Ge components.The structure of the Si_0.3Ge_0.7 JL-DGTFET device with the best performance parameters is obtained.The device's on/off current is increased by 1 orders of magnitude over Ge JL-DGTFET to 8×10⁴,and the subthreshold swing is 11%lower relatively,while the on-state current is 3 orders of magnitude higher than that of Si JL-DGTFET.A new Ge/Si heterojunction junctionless double-gate n-TFET structure is proposed.The advantage of the device is that the on-state current is high,I_on=1.6×10^-6 A/?m,and the off-state current is also kept at a low level,I_off=1.2×10^-10A/?m.The subthreshold swing SS is reduced to 83mV/dec,and the on/off current ratio reaches 1.4×10⁴.Therefore,the Ge/Si heterojunction plays a key role in improving the performance of Si Based junctionless TFET.On the basis of the above research,tensile stress is introduced into the global and local parts of Si JL-DGTFET and Ge/Si HJ-JL-DGTFET devices respectively,and their electrical properties are analyzed.Finally,the optimized tensile strain Si JL-DGTFET device is obtained,and its on-state current Ion is increased by 2 orders of magnitude compared with that without strain.In addition,the Ge/Si HJ-JL-DGTFET device with only 1%strain in the source area has been improved in all aspects,its on-state current is I_on=6.2×10^-6A/?m,I_on/off=3.6×10⁴,and the subthreshold swing SS=48mV/dec.