Characteristic Analysis And Optimization Design Of Junctionless Field-effect Transistors

Conventional metal-oxide-semiconductor field-effect transistors are based on the use ofsemiconductor junctions, which are capable of blocking and allowing current to flow with anapplied gate bias. When transistors are scaled down to nanoscale level, the distance betweenjunctions in transistors will reach dozens or even a dozen of nanometers, which bringschallenges for fabrication of junctions. Therefore, a new type of transistor without anysemiconductor junctions named Junctionless transistor is proposed. In nanoscale level,Junctionless transistors can suppress short-channel effect, drain induced barrier lowering,gated-induce drain or source leakage, so that transistors with shorter channels can befabricated.In order to gain great insight to junctionless field-effect transistors and further optimizeits properties, the basic conduction principle, main characteristics and the current andsubthreshold-region characteristics models of short-channel junctionless field-effect-transistors and benefits and limitations in the extreme size were discussed in this paper.According to shortages caused by different situations, three improvement programs wereproposed. Those three programs were verified by SILVACO simulation of specific double-gate and triple-gate or fin-structure junctionless field-effect-transistors. Moreover, methods ofoptimal design were given and final optimal parameters were obtained by analyzing andcomparing the simulation results to improve the behavior of junctionless devices further in theextreme size.