A Simulation Study Of Tunneling Field Effect Transistors

As MOSFET gate lengths are scaled below45nm, fundamental physical limitations are presenting barriers to further scaling. Among them, the most important one is the subthreshold swing (SS) limitation, that due to the thermal distribution of carriers, limits the rate at which a MOSFET can be turned on or off with respect to applied gate voltage. This means that as supply voltage are reduced, leakage power is increasing exponentially. Tunneling field effect transistor is proposed as a promising candidate for MOSFET in the future. It has a fundamental different working mechanism from MOSFET. While in MOSFET, current is formed by the diffusion and drift of carriers, current is formed by band to band tunneling in TFET. There is no exponential relationship between temperature and the current of a TFET. The subthreshold swing of a TFET doesn’t limited by the thermal distribution of carriers and can be smaller than60mV/dec. From this point of view, TFET can work at smaller gate voltage and have smaller leakage current which are suitable for low power applications. This thesis studies TFETs by simulation method in a commercial device simulator-APSYS.This thesis is focused on simulation of TFETs, including the simulation of LTFETs and VTFETs. TFETs is proposed as a promising candidate of MOSFETs in the future, early TFETs actually is a gate controlled p-i-n diode, the direction of band to band tunneling is parallel with gate-body interface and is called LTFETs. Both simulation and experimental results have been demonstrated the LTFETs can have smaller SS than60mV/dec. APSYS simulation verifies band to band tunneling current is the main current of LTFETs rather than diffusion-drift current. Structure parameters are optimized for LTFETs through APSYS simulation. Thin oxide thickness and large source doping concentration can supply a large ON current and a SS less than60mV/dec, about59mV/dec.A lot of simulation is performed on VTFETs in this thesis. Band to band tunneling direction in VTFETs is vertical to gate-body interface. Three types of SS are displayed according the "turn-on" sequence of the tunnel diode and NMOSFET in series can be seen in the simulation. The simulation shows that if the MOSFET turns on before the tunnel diode, the VTFET has a non-limited by thermal distribution small SS. If the tunnel diode turns on before the MOSFET, the SS of VTFET degrades dramatically and displays a MOSFET-like SS. The "turn on" sequence of the tunnel diode and MOSFET is determined by the design of n+pocket in the VTFET structure. This thesis proposed a design rule for such a VTFET, it is meaningful for reveal the device physics.At last, an exploratory study of threshold voltage of the tunnel diode in VTFETs is performed and analytical model for threshold voltage of tunnel diode is obtained and simulation is performed. It may be a reference for further study of threshold voltage of VTFET.