Development of a Deep Submicron Fabrication Process for Tunneling Field Effect Transistors

The requirements placed upon next-generation devices include high on-state current, low power supply voltages, and low subthreshold swing. Tunneling Field Effect Transistors (TFETs) have been of recent interest because they have the potential to fulfill these requirements. The TFET is a gated tunnel junction. The TFET operates by modulating the probability of band-to-band tunneling between the source and the channel of the device. When the tunnel transistor is off, there is a potential barrier between the source and the channel. The width of this potential barrier is large enough to prevent electrons tunneling from the valence to conduction bands, the result of which is a lower leakage current and improved power efficiency. The potential barrier narrows as bias is applied to the gate. When the applied gate voltage exceeds the threshold voltage this potential barrier becomes thin enough to allow for tunneling from the valence band to the conduction band. The tunneling mechanism allows the device to have a high on-state current and low subthreshold swing at low power supplies.;To date the majority of the work involving TFETs has been simulation-based. Unfortunately the models used in these simulations are deficient. The models require physical data for proper calibration*. The few experimental demonstrations of TFETs have not yielded a body of empirical data sufficient for calibration. This work intends to help provide that body of experimental data on gated and non-gated tunneling junctions in InGaAs. This work focuses on the development of a process to gate p-i-n junctions and extract the contribution of the gate on junction performance.;*Please refer to dissertation for references.