Research And Design Of Frequency Synthesizer Based On Cascaded PLL Architecture For 5G Communication

With the rapid development of the fifth generation mobile communication technology(5G)in the millimeter wave frequency band,people will get higher data rate and spectrum efficiency.In wireless transceiver,the local oscillator signal provided by frequency synthesizer is particularly important.The signal quality directly affects the bit error rate and power consumption of the whole system.In this paper,based on the 5G millimeter wave frequency division in China,the system structure and the innovative design and research of the phase-locked loop frequency synthesizer are mainly carried out.First,this paper investigates the research status of 5G millimeter wave frequency synthesizers and analyzes their advantages.By comparison,the existing problems of 5G millimeter wave PLL frequency synthesizer are summarized.According to the 5G communication protocol and the international advanced level of frequency integrator performance,the design structure and indicators are selected.With the help of MATLAB and other software,the system stability,optimal intermediate frequency and noise were considered.Finally,the parameters of each loop of the cascade phase locked loop were determined.Second,this paper adopts fractional frequency division in the first stage charge pump type phase locked loop(CPPLL),and the design emphasis of this stage is to reduce the output phase noise as much as possible.Based on this concept,a high precision charge pump is designed.By optimizing the size of the complementary differential switch transistor and adding the rail to the rail operational amplifier at the output,the current mismatch is reduced.Based on the Hajimiri phase noise model,a noise-shifting Colpitts VCO is designed.The effective impulse sensitivity function(ISF)is reduced by adding tail cross-coupling pairs to reduce phase noise.The divider chain is realized by 23 multi-mode divider and Sigma-Delta modulation.Third,subsampling phase locked loop(SSPLL)is used in the second stage.The loop includes subsampling phase detector,subsampling charge pump(SSPD/CP),in-phase injection coupled scillator(IPIC QVCO)and other circuits.In view of the tradeoff between the phase noise and the tuning range of millimeter-wave VCO,the transistors connected by four diodes are used to form a coupling network,which can generate quadrature signals while introduce small parasitism and noise at the same time.In addition,the differential inductor in the tank and the filter inductor in the rail are designed with high Q values,and the electromagnetic simulation is carried out.Finally,based on the optimization of the first-stage CPPLL and the second-stage SSPLL,the cascade phase-locked loop frequency synthesizer is realized.And complete the layout design and optimization,this scheme adopts SMIC 55nm CMOS process.The post-simulation results show that the current mismatch of the charge pump is less than 0.3%,and the current noise of the co-simulation with PFD/CP is-224.7d BA@100k Hz.The phase noise of the Colpitts VCO is-111d Bc/Hz@100k Hz and-133d Bc/Hz@1MHz when the tuning range is4GHz?4.64GHz.In the tuning range of 24GHz?28GHz,the quadrature phase precision of IPIC QVCO is less than 0.5°,and the phase noise can reach-114.4d Bc@1MHz and-135.2d Bc@10MHz.According to the post-simulation and electromagnetic simulation verification,all the indicators meet the design requirements.The final chip area is 1.75mm~2,the power consumption is 62.4m W,and the phase noise after fitting is-109.4d Bc@1MHz and-128.3d Bc@10MHz.The locking time is less than 5?s.