Study On A Stress Pattern For DDR Training

With the development of society,people's demand for data transmission and access speed of various electronic devices is increasing.The storage technology has developed from the previous SDRAM to today's DDR SDRAM,and has been iteratively developed to the fifthgeneration DDR5 SDRAM.The doubling of the signal transmission rate in each generation of DDR and high-density parallel wiring make the signal integrity problem more and more serious.Under the high-speed transmission of the signal,the inter-symbol interference(ISI)caused by loss and the crosstalk caused by multiple parallel transmission lines will cause serious distortion of the receiver signal and serious deterioration of the eye diagram.Therefore,in order to ensure the correct transmission of data,an effective link pressure test must be carried out.After the system is started,DDR Training will be conducted to find the best sampling center point for high-speed data transmission.DDR Training will use some specific patterns for link stress testing.The greater the pressure of the test pattern,the more it can stimulate the worse inter-symbol interference and crosstalk of the link.Then the trained sampling center point can guarantee the signal Achieve a lower bit error rate(BER)level during high-speed transmission.At the same time,the shorter the test pattern length,the user can get a more friendly boot experience.With the advent of DDR5,in the face of more serious ISI and crosstalk,the traditional test pattern appears to be inadequate.A pattern with a moderate length is difficult to put enough pressure on the link,and a too long pattern will cause The unacceptable test time makes it difficult to meet the needs of DDR Training.Therefore,how to design a stress pattern that can put more pressure on the DDR link and create a harsher test environment on the basis of ensuring that the length of the test pattern is limited has become a difficult point.In response to the above problems,this thesis first introduced the basic knowledge of DDR and related signal integrity issues,and detailed the specific process of the DDR Training algorithm;then,this thesis proposes a pressure pattern for high-speed parallel link testing.According to the noise characteristics in the high-speed parallel link,the stress pattern is divided into two parts: the stress pattern of the victim line which can excite the worse ISI,and the stress pattern of the aggressor line which can excite the worse crosstalk,the combination of the two can exert enough pressure on the high-speed parallel link to optimize DDR Training Sampling center point to ensure a lower bit error rate level during data transmission.Through the simulation and actual test of the two links under different data rates,the effectiveness and superiority of the proposed stress pattern compared with the traditional test pattern under different scenarios are proved,and as the data rate increases,the pressure is raised,the advantage of the stress pattern is more obvious,which can put more pressure on the link;finally,this article developed a pressure pattern generation tool SP_Tool based on Matlab,which can generate any order of PRBS patterns,VMRQ-PRBS patterns and the stress patterns mentioned in this thesis,and supports encoding of existing pattern sequences,to generate the corresponding attack line pattern.