10Gbps Serdes Signal Integrity Research For Backplane System

The electronic products are experiencing a rapid development toward high density and high speed applications.The speed limitation of I/O bus transmission has become a key bottleneck to system bandwidth expansion.An important factor affecting the speed increase is the signal integrity of the communication bus.In order to meet the increasing demand for bandwidths,today more and more communication system adopts the backplane & daughter cards system architecture,in order to achieve the long distance inter-board signal transmission,the high speed serial bus need to transmit through variety medias,the transmission speed and distance are limited by the poor impedance continuity and high-frequency loss when adopting traditional design method,which brings great challenges to the system signal integrity design.Based on the combination of theory and simulation,this paper completes a 10 Gbps SRIO backplane serial design with a total length of 32 inches.The design rules obtained by simulation are used to guide the design.Firstly,the details of the transmission channel are optimized: the design scheme of differential coupling mode,phase skew compensation,segment over split reference plane and AC coupling capacitance optimization is proposed.Secondly,different kind of differential vias are simulated and compared to find the less loss via geometries.The via stubs and the non-functional pads are analyzed,and the signal path return improvement of the ground stiching vias is studied.Then,the influence of copper foil roughness,dielectric constant,loss factor and glass fiber effect was studied.Finally,the importance of pre-emphasis and equalization for long-distance 10 Gbps serial links transmission is discussed.The experiment of this thesis is relied on the field and circuit co-simulation method,using Ansys high frequency electromagnetic simulation tool SIwave and Mentor simulation tool Hyperlynx to perform modeling and simulating of the passive link details.By comparing the parameters of the simulation results,it is concluded that the transmission channel with optimized design has greatly improved the insertion/return loss and the continuity of impedance,so that the S parameters of the entire channel can meet the 10 Gbps SRIO protocol requirements.The insertion loss is improved 10.92 dB,and the return loss is improved 16.08 dB at Nyquist frequency.Then the S parameters of the optimized passive link are imported into simulation tool ADS to build a complete circuit link to perform time domain simulation,the results show as an eye diagram with the width of 44.5ps and the height of 170 mv.By adopting pre-emphasis and equalization technology,the eye width and eye height can be further increased to 69 ps and 439 mv,which is perfectly meet the chip sampling requirements.Based on the actual project design,this thesis validates the effectiveness of the transmission channel optimization measures in both time and frequency domain,and obtains suitable scheme for the high-speed circuit design.It aims to provide the instructive method for the long distance high-speed signal integrity design in the future.