Signal Integrity Design Of High-speed Serial Link Over Backplane At 25 Gbps

With the rapid development of the Internet and the fast increase of the data size, new generations of core switches with larger exchange capacity and higher transmission performance are needed for data centers. At present, researches on bandwidth upgrading of core switches are focused on the design of high-speed serial link over backplane at 25 Gbps, which is the object of this study.High-speed signal is influenced by attenuation, reflection and crosstalk during the transmission, which will compromise signal integrity. It will be more serious with the increase of signal speed and channel complexity. To eliminate or minimize these problems and make sure of the accurate transmission of 25 Gbps high-speed signal, signal integrity design of high-speed serial link is carried out on the basis of both passive and active design in this article. Furthermore, some optimization techniques for passive channel design, chips selection and optimal settings are proposed and discussed to improve the overall performance of the high-speed system based on the results of the simulations and experiments.A Ser Des selection is offered at 25 Gbps with its SI configuration analysed. And its maximum driving capability under normal temperature is evaluated by experiment. According to recent studies, some jobs about high-speed passive design are accomplished in this article, including laminate design, AC coupling capacitor selection, via design and connector selection. And the antipads optimization of vias is discussed. With the help of an equivalent differential vias model, the parameters of antipads are able to be estimated before simulation, which helps to improve the efficiency of the procedure. Moreover, four different kinds of antipad patterns are designed and compared based on the simulation results. It also investigates approaches used to reduce the impedance discontinuity caused by AC coupling capacitors. And five kinds of void structures of the reference plane are tried in this article and explored through simulation. Furthermore, the active optimization scheme is determined after the comparison among three kinds of repeaters. In this article, a comparative analysis on different CDR architectures of retimers is carried out. And there’s a research on the usage of retimers from the perspective of SI performance. After that, the specific chip solution is determined for the full-link application. Next, it has discussed the method for optimal parameter configuration using Green Box, in which parameter convergence means and stacking method are utilized.Finally, a system platform is built to do the full-link tests. The results show that the 25 Gbps high-speed serial link over backplane well meets the requirements, and the system operates steadily. This article offers end-to-end solutions for the signal integrity design of 25 Gbps high-speed serial link over backplane, and provides theoretical guidance for the practical engineering.