Design And Implementation Of Multi-channel NAND Flash Controller Based On PCI Express Interface SSD

With the advent of the era of big data,the demand for data storage has skyrocketed.NAND Flash is becoming the current mainstream storage medium due to its high performance,high density,non-volatility and low power consumption.The capacity and speed of a single NAND Flash is far from reaching the high-capacity and high-speed host interface requirements of SSD.It is commonly used in SSD to integrate multiple NAND Flash chips and control multiple chips to perform read and write operations in parallel to meet the needs of solid state drive's design requirements.At present,SSD with PCIe interfaces has entered the enterprise market and consumer market.Compared with traditional SATA interface SSD,it has the advantages of low latency,high performance and low power consumption.Therefore,designing a multi-channel flash memory controller responsible for scheduling operations of multiple NAND Flash chips to be suitable for PCIe interface SSD has important research significance.The design of the multi-channel flash memory controller is completed in this thesis.The multi-channel flash memory controller,the PCIe controller and the DDR controller together form the SSD controller.The multi-channel flash memory controller receives the commands and data from the PCIe controller,and completes the access to the NAND Flash and DDR controller through the analysis and reorganization of the commands and the cache movement of the data.There are 16 NAND Flash channels and one DDR channel in the multi-channel flash memory controller.The NAND Flash channel converts the command to access the NAND Flash into the read and write sequence of the NAND Flash interface to complete the access to the NAND Flash.When a read and write command is received,it initiates a read and write address request and a read and write data request to the PCIe controller or DDR controller.The DDR channel converts the command to access the DDR into an AXI interface timing sequence and sends it to the DDR controller to complete the read and write access to the DDR by the PCIe controller and the NAND Flash channel.The 17 channels of the multichannel flash memory controller designed in this thesis can process host commands in parallel,and different chips of NAND Flash can be accessed in parallel in the Flash channel.The PCIe controller and the Flash channel are accessed the DDR controller in parallel by the DDR channel.Thus,the efficiency of the host's access to the SSD controller is improved.The multi-channel flash memory controller designed in this thesis is divided into channel arbitration module,control interface module,data management module,Flash command processing module,DDR channel module and Flash controller IP.The channel arbitration module is responsible for issuing commands to the corresponding channel and receiving read and write requests from the channel.The control interface module,the data management module,the Flash command processing module and the Flash controller IP form a Flash channel,which receives commands and data to complete the access to the NAND Flash.The read and write access of the PCIe controller and the Flash channel to the DDR controller is completed by the DDR channel.The design requirements of the above sub-modules and RTL design have been accomplished.The design of the multi-channel flash memory controller is completed,the verification function points of the multi-channel flash memory controller are extracted.The UVM verification platform design of the multi-channel flash memory controller is completed.The verification platform is based on the standard components of UVM,and the scheduling of the excitation of each component is realized through the Virtual Sequence.And based on the UVM verification platform to complete the functional verification of the multi-channel flash memory controller.The verified multi-channel flash memory controller is integrated into the SSD controller,and the UVM verification environment of the SSD controller is built to simulate the whole SSD controller.The UVM verification environment integrates the standard NAND Flash model and DDR SDRAM verification IP to correctly simulate the behavior of the interface IP in the PCIe controller and complete the functional verification of the SSD controller.It has been verified that the designed multi-channel flash memory controller works normally in the SSD controller system,and the design and implementation of the multi-channel flash memory controller have been accomplished.