FPGA Implementation Of NAND Flash Controller

With the development of science and technology,more and more electronic products such as mobile phones and ipad have become more and more demanding on the storage and quality of flash chips.Flash memory has the advantages of low manufacturing cost,fast rewriting speed,large storge capacity,etc.It is widely used in the field of data storage.The controller realizes functions such as reading and writing to the memory.In the current integrated circuit,it is of great significance for reducing the circuit area,reducing the system cost and improving the reliability.FPGA verification is performed in a real physical environment,and problems can be discovered and resolved before streaming.First,this article discusses the internal structure of NAND Flash.The internal unit structure of NAND Flash and the storage of NAND Flash in the market are introduced.The read and erase operations of the memory are described.Second,this article also explains the basic operation timing of different operations.The timing requirements for each operation are analyzed,as well as the difference between synchronous and asynchronous.Finally,in order to solve the architecture design and hardware testing problems of NAND flash memory controllers,this paper presents a design scheme of NAND flash memory controllers,and builds an efficient hardware test platform based on upper computer control.The architecture is based on the ZYNQ soft core,which supports both asynchronous and DDR2 modes.The operating commands and data from the upper computer are transmitted to the controller through the GPIO bus.The controller then generates the control signal to the chip.The test platform is based on the ONFI 3.2 protocol and utilizes the LDO.Implement the voltage turn-on requirements for Vcc and Vccq to reach the Flash chip turn-on condition.On the basis of fully emulating the timing and function of the verification controller,the board-level verification is performed using the built hardware test platform.The final result shows that this design can meet the NAND flash drive control requirements.