Bch Code-based Nand Flash Controller Design

As the growth of smart phone, it needs more and more data storage device. NAND Flash is famous for it's non-volatile and smaller size compared with other data storage device, also it is much faster to read and write, so it is wildly used in the SoC devices.In order to reduce the price per bit of data storage device and to increase storage density, the industry's two main methods is Multi-Level Cell (MLC) technology and process to reduce the number of dimensions (60nm and 45nm).Relative to the Single-Level(SLC) one bit per unit. MLC can store two or more bits in a floating gate, but this makes the space between adjacent data voltage smaller and the reliability variation decrease, so it need to control the charging voltage of each memory cell of MLC.BCH error correction code is the ability to control the random error correction, it is a subclass of cyclic codes. A commonly used error correction code (such as Hamming code) is not suitable for the case of MLC. BCH error correction codes have more.This article discusses the mainstream NAND Flash (based on Samsung) structure and timing characteristics of interface to read and write and erase, and a rough introduction to the ARM based embedded structure. NAND Flash Controller based on AMBA bus. This paper forcus on the actual needs of the algorithm implemention and optimization, for the actual needs, it can be used in 512Byte,1KB,2KB,4KB,6KB and 8KB code based BCH's NAND Flash controller structure.We use two methods to validate the NAND Flash Controller design, one is function simulation and the other is FPGA simulation, the result shows the design is correct.The NAND Flash Controller design bases on the actual needs of a company. It fully meets the company's needs.