NAND Flash Controller Design And Co-Verification With Software And Hardware

With the rapid development of electronic products, the function of consumerelectronics products are becoming more and more complicated, and the requirement ofits memory capacity is becoming more and more big. One type of consumer electronicproducts, portable multimedia player requires that the memory should be small size andlow power consumption. The NAND FLASH has been used in electronic productswidely with its high-capacity, small size, low cost and low power consumptioncharacteristics. Therefore, it becomes a tendency that the NAND FLASH controller isintegrated into the SoC system.This paper analyzes the NAND FLASH storage principle, the architecture of theNAND FLASH device and the operation sequence and timing of read write and eraseoperation at first. According to the feature of NAND FLASH device, the paperdiscusses a design of AMBA AHB bus NAND FLASH controller and software andhardware co-verificaiton base on FPGA.For the controller design, in order to overcome the bit-flipping characteristics ofMLC NAND FLASH device, the BCH module is integrated into the NAND FLASHcontroller. And also use the serial data converted to parallel data computing technologyto optimize the BCH calculation. In order to accelerate the speed of access to the NANDFLASH device, the controller could work at auto mode according to the usual read andwrite sequence and timing of the NAND FLASH device, when access multiple NANDFLASH chip, the interleave mode make use of each device’s busy time, and improve theoverall read and write operation efficiency. In order to make the controller can beapplied to a variety of NAND FLASH device, the controller supports NAND FLASHdevice access timing parameters CPU configuration, and also support for multiple pagesize and variety of error correction specifications for different NAND FLASH device,and try to make the shared hardware to save the controller area.For the verification of NAND flash controller, this paper discusses the functionalsimulation and the FPGA-based software and hardware co-verification. After thefunctional simulation, in order to verify the NAND FLASH controller fully and realistically, the FPGA based software and hardware co-verification is used. At first,integrate the NAND FLASH controller into the ARM core SoC system, synthesis anddownloaded the bit file to Xilinx Virtex-4FPGA chip, and then, write the C testprogram in the ARM intergrated development environment. So that the NAND FLASHcontroller is verified by software and hardware.The design of a high preformance FLASH controller with error correctionfunction has a borad pratically value in engineering.