Ata Flash Disk Encryption Controller Research And Design

While the implementation of Flash memory can rapidly develop, the design of Flash memory controller system will be a research field. At the same time, flash memory should be used widely in the security department, such as government office and the department of defense because of its peculiarities. As a result, the security of data in Flash will be a serious problem. According to advanced designs of Flash memory controller and cryptological algorithms, ATA Flash disk encryption controller is proposed in this dissertation, which consists of a FPGA processor with encryption function based on IDE interface.At the beginning, the design of ATA Flash disk encryption controller is analyzed and presented, while we do some research on arithmetic operations in the finite field. And then we are focused on IDE interface controller in which commands of the host throughout IDE interface are parsed and every accessing address is transformed into LBA. In this paper, we propose a new design for the flash translation layer, called Configurable NAND Flash Translation Layer which provides a way for different vendors to tune up the system for their needs. To reduce the main-memory space requirements for flash memory management, four management units, cluster, region, segment, and frame. Cluster is used to manage the logical space. Region is designed for mapping from the logical space to the physical space. Segment and frame are introduced to manage the physical space. Flexibility in mapping any LBA to any page in any block on flash memory is realized. Under different settings of the cluster size, the region size, and the segment size for FTL, the impacts on the performance are explored. Finally, after an efficacious pipelined AES-128 unit is presented, a series of experiments is conducted to provide insights into performance of the controller system, compared with existing implementations.