Design And Implementation Of SOPC-Based Multi-channel NAND FLASH Controller

SSD, Solid State Disk, is the hard disk which consists of main control unit, solid-state storage unit (DRAM or FLASH chip).It completely abandon the traditional mechanical structure, and uses DRAM or FLASH as data storage, having lots of advantages and high storage performance with high growth potential in the field of storage technology compared with traditional drives.SSD main control unit plays an important role in the SSD. The main control unit with high performance is the soul of the whole SSD system. It mainly including host interface module, data caching module, flash memory interface module, etc. The main content of this paper is the design of FLASH memory interface module, namely the NAND FLASH controller design, which supports the Legacy SDR and Toggle DDR standard. And it may control the FLASH array through the multi-channel management.The author make a reasonable structure design and module partition for the NAND FLASH controller. It mainly consists of bus interface module, the cache module, choice of the cache module, FLASH SDR interface module, FLASH DDR interface module and ECC error detection and correction module. This Paper mainly includes the state machine design of two interfaces, the support for the DMA, the the underlying drivers design in the NIOS II CPU, multi-channel management, etc. The controller is a user-defined component hanging on the Avalon bus, one controller to one channel. It can be used to realize pipelining operation in the single channel and multi-channel parallel operation under the control of the CPU. This design can support different page sizes of FLASH devices with modifying the corresponding parameters.The whole design is designed based on SOPC system, including the hardware design in Quartus II, software driver design in NIOS Eclipse. A single NAND FLASH Controller costs980FPGA logic units. The ModelSim simulation results show that write performance is5.77MB/s and read performance is18.8MB/s of single channel single-chip FLASH, and write performance is16.43MB/s, read performance is32.12MB/s of single channel4lines. N times the read and write performance of single channel can be achieved by using N channels. This design can be widely used in Solid State Disk and other high speed and large capacity FLASH storage system with a broad application prospect.