The Verification Of NAND Flash Controller Based On VMM

With the development of semiconductor technology, the scale of the integrated circuit design becomes larger, and chip design has become increasingly complex, the work of integrated circuit verification becomes more and more difficult. Verification is an essential part of the integrated circuit design, it guarantees that the function of chip design can meet the requirement of specifications and reduce the frequency of taping out caused by function defects, then it can shorten time to market. But the development of verification methodology is much slower than it of design. Recent studies indicate that the verification work for complex logic chip takes about 60%~70% in the whole chip research period. However, traditional verification methods are difficult to satisfy the verification of the complex chip. Therefore, it will be an important direction for verification engineers to research efficient, automated, reusable verification methods.Based on VMM verification methodology, this paper builds a verification environment for NAND Flash controller which support asynchronous, ONFI and Toggle NAND Flash interface standards. First, VMM is a hierarchical test platform based on System Verilog language,which supports the constraint random stimulus and coverage-driven verification, and the function of automatic comparison. This paper analyzes the work protocol of asynchronous, ONFI and Toggle NAND Flash interface standards, then the main function verification points are extracted, which is based on the combination of architecture and functional characteristics of NAND Flash controller. This paper proposes a reusable verification platform structure aiming at the function point, and then the function and achieving methods of each verification components are discussed in detail. In this paper, the test function points are verified by creating constrained random stimulus, and builds the functional coverage group. In the validation process with functional coverage as the guidance to ensure the verification work, and it can add directional test cases to the non-covered function points combined with the statistical results of three kinds of coverage. And the method of automatic comparison between the results of the reference model and the design are used to improve the efficiency of verification. Combined with the directed methods and random methods, the design under test can achieve more scenarios. Using the constraint random stimulus methods improve the automation of the platform. Then the paper uses VCS to complete the simulation work and DVE to debug. The simulation results are analyzed by the generated files and waveforms in the simulation process.Finally, through the analysis of the functional simulation results and coverage report, we communicate with the designer the functional defects that we find in the simulation process, and timely modify the bug to ensure the NAND Flash controller can meet the design specification. The coverage rate has reached the requirement of target, the functional coverage reaches 100%, the code coverage reaches 99.15%. The verification platform built in this project has a strong reusability and can be applied to other NAND Flash controller projects, greatly improves the efficiency and shorten the development cycle, fully embodies the characteristics of VMM verification methodology.