A 14 Nm FinFET Technology Based High-speed SRAM Design

With the development of big data,artificial intelligence,and 5G technology,it is necessary to make chips with faster speed,lower power consumption,and better performance.It accelerates the development of CMOS technology urgently,so that the size of CMOS is shrinking.Thanks to the continuous reduction of planar MOS size,the chip under the advanced process node shows better performance of lower power consumption and lower price.SRAM is an important part of SOC.However,the speed of SRAM can hardly keep up with the performance improvement of CPU only by means of process improvement,so the design method of high-speed in SRAM has been one of the hot issues in the field of memory design.In this paper,two methods are used to optimize the SRAM speed.First,SMIC 14nm FinFET device was used for circuit design.Another point is the use of two-stage pipelined architecture design SRAM memory.By analyzing the data transmission path in SRAM of traditional architecture,finding that both read and write operations need to locate the SRAM cell through the decoder,but the delay of decoder accounts for 50%of the total delay.In this case,reducing the delay of decoder can effectively improve the speed of SRAM.Based on this theory,a two-stage pipelined SRAM architecture is proposed.Traditional SRAM is divided into two parts:decoder part and read-write path part and connected by register.Compared to traditional SRAM,the delay of pipelined SRAM is only equal to the overall delay of SRAM in original architecture minus the decoder delay,and only register delay is introduced.In order to make the pipelined SRAM work faster,a control circuit of sensitive amplifier is designed.it can turn off the read-write path of word line and bit line to reduce the power consumption and avoid noise generation.A self-timing clock is designed which refer to the data transmission path.A decoder with reset feature is designed to avoid the problem of redundant operations in pipelined SRAM.A write-path circuit with pipeline characteristics is designed.Through the use of the above technology,not only the Two stage pipelined SRAM circuit was designed,but also the power consumption is optimized.In this paper,two high-speed SRAM circuits were design using SMIC 14 nm FinFET,respectively using traditional architecture and two-stage pipeline architecture.Results show that the access time of high-speed SRAM based on traditional architecture is 271ps,while that of SRAM based on two-stage pipelined architecture is 203ps.Results compared shows that SRAM designed by means of traditional high-speed design methods speed increases by 11.28%averagely.the SRAM in FinFET technology but using pipeline architecture speed increased by 25.1% again.