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The Design Of ViSAR Signal Generation And Acquisition Processing Component

Posted on:2022-08-03Degree:MasterType:Thesis
Country:ChinaCandidate:N N ZhengFull Text:PDF
GTID:2518306602490064Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
Video synthetic aperture radar which developed from synthetic aperture radar is a new kind of imaging radar.In addition to the advantages of SAR's high resolution and long-distance microwave imaging,ViSAR can also continuously monitor the observation area in real-time in the form of dynamic video,so as to achieve the recognition and tracking of moving targets in the scene.ViSAR has the characteristics of high frame rate,high resolution,and low delay imaging,which puts forward higher requirements on the radar digital processing system.Traditional ViSAR systems usually use DSP+FPGA architecture.This architecture makes the ViSAR system huge in size and high in power consumption,And it's hard to meet the needs of current ViSAR airborne platforms.Aiming at the needs of the ViSAR project and the development trend of radar signal digital generation and processing,this paper focuses on the digital generation of ViSAR signals and the acquisition processing technology of highspeed radar signals.Combining parallel DDS technology and FPGA device reconfigurable technology,a highly integrated,low-power ViSAR signal generation,acquisition processing component is designed.This kind of ViSAR signal generation and acquisition processing component can not only achieve the functions of ViSAR signal generation,signal acquisition,and data preprocessing,but also complete the control and data communication of the peripheral components of the ViSAR system.The main work of this paper is as follows:1.Research the related technical theory of ViSAR system.By deriving the azimuth and range resolution of the SAR,the high-resolution imaging principle of the SAR is explained;the time-frequency characteristics and simulation generation methods of the chirp signal are analyzed,and the advantages and characteristics of the chirp signal are explained;The related theories of DDS technology are studied,and parallel DDS signal generation technology is proposed.Aiming at the problems of high data throughput rate and computational complexity of ViSAR received signals,two methods are introduced to achieve digital down-conversion technology,and is specially optimized for FPGA implementation.2.The overall hardware system of the ViSAR signal generation and acquisition and processing components is designed.By analyzing the technical index requirements of the ViSAR,the overall hardware scheme of the ViSAR signal generation and acquisition and processing components was given.The hardware solution uses a single-chip FPGA as the main controller,and achieves the functions of ViSAR signal generation,IF signal acquisition through the cooperation of various chips such as high-speed ADC and high-speed DAC.According to the requirements of technical indicators,the hardware scheme introduced in detail the device selection and hardware circuit design of the core module of the ViSAR signal generation and acquisition processing component.At the same time,according to the principle of electromagnetic compatibility,the layout of the printed circuit board is introduced,and reasonable layout and wiring are used to improve the system performance under the premise of satisfying the function.3.Completed the logic software design and FPGA implementation of the ViSAR signal generation and acquisition processing components.According to the index requirements,a ViSAR signal generation module,an IF signal acquisition and processing module,and a system controller module are designed.The ViSAR signal generation module is based on the parallel DDS digital signal synthesis technology,which achieves the signal output in the Lband,with a bandwidth of up to 600 MHz,high frequency modulation linearity and excellent harmonic and spurious suppression performance.The IF signal acquisition and processing module achieves high-speed acquisition and reception of IF signals,with a sampling rate of500 MSPS,and reduces the data rate of the received signal by optimizing the digital downconversion technology,and reduces the computing pressure of the processor.Based on SOPC technology,the system controller achieves the control of each module of the ViSAR and the data communication of each peripheral component.
Keywords/Search Tags:ViSAR, FPGA, parallel DDS, high-speed DAC, SOPC
PDF Full Text Request
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