Research And Implementation Of High Speed Parallel Mult Iratealgorithm

With the rapid development of digital signal processing,signal processing,encoding,transmission and storage need more and more workload.In order to save storage space and calculate the workload,the multi sampling rate digital signal processing came into being.The system can reduce the transmission rate,reduce the storage and reduce the computational complexity.FPGA sets the functions of acquisition,control,processing and transmission in a chip,which has high programming flexibility,short development cycle and high flexibility in parallel computing,so FPGA has been widely used in digital signal processing.In this paper,FPGA is used to deal with the commonly used numbers in multirate digital signal processing.In addition,cascaded integral comb CIC and parallel FIR are studied.The main contents and results of this paper are as follows:Firstly,a fully parallel FIR filter structure based on FPGA platform is proposed,which can greatly improve the computing power of the filter.Compared with the traditional serial filter structure,the speed of the parallel structure can increase N times,and the operation delay will be reduced at the same time.In addition,the operation throughput is greatly improved.Through structural transformation,the direct structure of FIR filter is transformed into a full parallel FIR filter structure.The corresponding registers are inserted after the adder and multiplier are inserted to form a multi-level flow structure.The filter performance is analyzed by the network analyzer,and a single filter is completed in a single clock cycle.The fixed-point parallel filter is implemented in cycolone III series chip of Altera company.Secondly,on the basis of FIR filter,a novel semi parallel FIR filter design method is proposed.This method has good performance,through optimization,multiple filter modules can be placed in a FPGA module,and it is implemented on the Cyclone III chip of Altera company.The input bandwidth of the signal is related to the number of the designed taps.According to the difference of the number of taps,the resource and speed can be effectively integrated in order to obtain the maximum efficiency.Finally,the cascade integrated comb CIC filter is considered,and the CIC filter is cascaded by the integrator(Integrator)and the comb(Comb).According to the different structure,the function of decimation(Decimation)and the interpolation(Interpolation)can be realized separately.The combination of CIC filter and HB(Half Band)filter can achieve channel extraction with large dynamic range and high multiplier.Based on the analysis of CIC filter,this paper proposes an interpolation CIC filter parallel processing algorithm,which has been verified on FPGA and implemented high-speed interpolation filtering operation.In addition,this paper analyzes and verifies the non recursive parallel structure of CIC filter extraction,and determines the direction for further research.