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Design Of Temperature Self-refresh Circuit With Test Mode For DRAM

Posted on:2022-01-13Degree:MasterType:Thesis
Country:ChinaCandidate:C LinFull Text:PDF
GTID:2518306602466514Subject:Master of Engineering
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Compared with other components in electronic system,storage devices have been the bottleneck to overall performance improvement,and DRAM as the main memory has been a research hotspot for a long time.Thanks to the special transistor capacitor structure of its memory cell,DRAM can achieve high integration and low power consumption.But also because of the leakage current of the transistor in the memory cell.Therefore,it is necessary to keep the stored data stable through continuous refresh.The magnitude of the leakage current of a DRAM memory cell is a decisive factor for its data retention capability.As the temperature rises,the leakage current will increase,and the retention time of the memory cell for data is shortened.Conversely,the retention time of the memory cell for data grows.DRAM memory arrays rely on external circuits to provide appropriate refresh signals.The refresh signal frequency should meet the requirements for stable data storage and also minimize the power waste caused by refresh in the storage array.Appropriate refresh frequency management is the key to balance DRAM performance and power consumption.This paper designed a new DRAM temperature self-refresh circuit based on LPDDR5 protocol.The circuit is constructed with submodules such as a low temperature coefficient oscillator,a sensitive temperature sensing module,and a controllable clock divider.This circuit provides more refresh frequency options over a wider temperature range than a temperature self-refresh circuit constructed based on MOSFET threshold voltage temperature characteristics,and makes it easy to report the real-time temperature of chip operation to the DRAM controller.The temperature self-refresh circuit in this paper contains a temperature sensing module based on a voltage comparator.It has a temperature measurement accuracy of 2.5°C,a measurement range of-40°C to 160°C,and outputs the temperature in digital form.By default,the self-refresh circuit outputs six different frequencies of self-refresh signals based on the measured temperature.The shortest period of the self-refresh signal is 0.96?s and the longest period is 15.36?s.The self-refresh signals provided by the different frequencies can meet the data retention refresh requirements of the storage array at different temperatures and reduce the chip power consumption as much as possible.In order to avoid the phenomenon of "missed refresh" when the self-refresh enable is exited,this circuit supports the new optional function optimized operating mode in the LPDDR5 protocol.In order to facilitate the later inspection of defects that may be introduced in the chip manufacturing process,or adjustment of some undesirable performance parameters,this article adds a test mode circuit to the temperature self-refresh circuit.Through the test mode circuit,the function of the temperature self-refresh circuit can be fully tested to ensure that the temperature read out and the self-refresh signal generated are correct.When the readout temperature of the temperature sensing module deviates from the actual temperature.The test mode circuit can adjust the readout temperature with a slope from-10.5% to 12% in steps of 1.5%,and adjust the position from-40°C to 38.75°C in steps of1.25°C.Clock management through the test mode circuitry autonomously reduces the clock frequency to decrease the power consumption of this circuit after the readout temperature has stabilized.Or manually configure the test clock for this circuit during the test.The test mode circuitry also includes the management of the frequency of the generated self-refresh signals.It is possible to modify the frequency of the self-fresh signals corresponding to a certain temperature range,or to alter the temperature range of the self-fresh signals corresponding to a certain frequency,or even to change the self-fresh signals regulated by the temperature auto to manually configured self-fresh signals.The adjusted self-refresh signal is changed to a manually configured self-refresh signal.The frequency selection scope of this temperature self-refresh circuit is greatly enriched.The circuit designed in this paper uses a mixed-signal simulation platform based on VCS-Fine Sim.It is verified that this temperature self-refreshing circuit and each sub-module meet the design requirements.Its readout temperature and the generated self-refresh signals are stable and reliable,and the test mode circuit is effective for functional testing and performance adjustment of the temperature self-refresh circuit.
Keywords/Search Tags:DRAM self-refresh, LPDDR5, Temperature self-refresh circuit, Test mode circuit
PDF Full Text Request
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