Designing 2T-SRAM And Improving Refresh Clock Circuit

With improvement in semi-conductor manufacture process, SoC is increasingly popular for designing integrate circuit, in which embedded memory is playing more and more important role. About 90% silicon area of SoC will be taken up by a variety of embedded memory in 2010 year. SRAM and DRAM are two most important embedded memories with which we are familiar. SRAM can operate in relatively high frequency, but more silicon area overhead id needed to manufacture. By comparison, DRAM needs small silicon area, however, its working speed is low. Recently, it becomes a new direction to develop low cost, low power consumption and high speed of embedded memory to meet the requirement to high performance SoC.This dissertation introduces a new memory, called 2T-SRAM that combines the high integration characteristic of DRAM and the high-speed characteristic of SRAM and makes it possible to meet the requirement to designing new memory. In our dissertation, we details the design of memory cell, array layout, decoding circuit and sense amplifier. We present the discussion about the traditional refresh clock generation circuit, and the new design to improve the refresh clock generation circuit from the angle of low power consumption, low-cost and difficulty of implementation. The proposed refresh clock generation circuit consists of temperature adjustment circuit, voltage detection circuit, clock output circuit and feedback circuit, which can effectively reduce memory refresh current. The design for the three parts of circuits is described in detail in this dissertation. Circuits are optimized based on taking consideration of the restrictions in silicon area, power consumption. Finally, the designed 2T-SRAM and new refresh clock generation circuit are simulated and the results are analyzed.The design presented in this dissertation is implemented based on the UMC 0.18um standard CMOS technology. The simulation results show that the design is accord with the requirement. We also present the layout design for 2T-SRAM cells. More works are needed to do in the future to improve further the performance of the proposed 2T-SRAM cells and its refresh circuit.