Research And Fpga Implementation Of Low Density Parity Check Code Decoding Algorithm In 5G System

The decoding performance of Low Density Parity Check(LDPC)code is close to the Shannon limit and the code is one of the best channel coding techniques,and the5th-Generation(5G)needs an excellent channel coding technology to support its services.In 2016,LDPC was determined as a coding scheme of the data channel in the5 G enhanced Mobile Bandwidth(e MBB)scenario.The decoding algorithm of LDPC code in 5G standard are mainly in this thesis,and the design and implementation of 5G LDPC decoder are completed based on the improved algorithm optimized from the existing algorithm.The origin of iterative formula of LDPC Belief Propagation(BP)algorithm is analyzed in this thesis from the perspective of probability theory,and the evolution process of BP to Log-Likelihood Ratio(LLR)BP algorithm is deduced in detail with other simplified algorithms.By analyzing the variation of normalization factor of irregular LDPC codes with the degree of check node,Degree-Based Normalized Min-Sum(DB-NMS)algorithm is proposed.When DB-NMS is applied in 5G LDPC,the appropriate normalization factor is determined according to the iterations of previous group and the iterations of current group.According to the simulation results,the proposed algorithm can achieve a maximum gain of about 0.13 d B in bit error ratio and about 0.15 d B in block error ratio compared with Density Evolution Min-Sum(DE-MS)algorithm,which proves that the proposed algorithm can improve the reliability of the system.In terms of complexity,DB-NMS algorithm only adds two comparison operations at the update of check nodes compared with DE-MS and Normalized Min-Sum(NMS)algorithms,which is realizable.Considering the tradeoff between throughput and resource consumption,the proposed decoder adopts the combination of layered scheduling and partial parallel decoding structure.The posteriori information storage unit stores information based on the lifting size,so as to ensure that the posteriori information participating in the update does not cross group.A tree structure comparator and a single bit mode are applied to the node update unit and the index of minimum of comparator "IDX" respectively.According to the change law of fixed-point normalization factor and information multiplication,the multiplication in update unit is transformed into shift and addition operation,which reduces the resource consumption.According to the characteristics of5 G base graph,only the first 1536 check equations are used by the designed check unit,which reduces the design difficulty of the check part,and does not affect the error correction performance.Finally,the Field Programmable Gate Array(FPGA)implementation of 5G LDPC decoder is completed,and the function of the decoder is verified by using Vivado and Modelsim platform.When the base matrix is selected as basic graph 1,the lifting value is 384,and the code rate is one third,the throughput of the decoder can reach 969.55 Mbps at 150 MHz clock frequency,so the designed decoder can meet the throughput requirements of the project.