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The Research On Construction, Decoding Algorithms Of LDPC Codes And Its Implementation

Posted on:2012-11-04Degree:MasterType:Thesis
Country:ChinaCandidate:M X LiFull Text:PDF
GTID:2218330368987767Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
LDPC codes were proposed by Gallager in his doctor paper in 1962. Because of its near Shannon limit performance and low complexity, it draws much focus in recent years and become the most competed candidate to 4G communication standard. QC-LDPC codes are a branch of LDPC codes and their H matrices are consisted of many sub-matrices which are all permutation matrices with the same size. The encoder or decoder of QC-LDPC codes can take parallel or partly parallel manner and is easy to implement in hardware.In this paper, we first introduced LDPC codes and their encoding, decoding and construction algorithms simply. Then, after studying the construction algorithms deeply, taking the triangular and dual-diagonal matrix, QC-LDPC codes construction method based on PEG algorithm, the density-evolution theory and the feature of QC-LDPC codes, we constructed an irregular QC-LDPC code with length 2304 and rate 1/2. We also estimated the minimum-distance of our QC-LDPC code.We then simulated our QC-LDPC code using the llr-bp, Min-Sum, NMS and OMS algorithms and compared with another two QC-LDPC codes. When simulating the NMS algorithm, after setting the offset factor to different values and comparing the results, we found that the best factor value was related with SNR value. According to the fact, we proposed a so-called Subsection Normalized Min-Sum (SNMS) algorithm. The SNMS is little more complex than the NMS and the performance arises obviously.At last, we discribed the encoder and decoder of LDPC codes using Verilog language in FPGA. The encoder used cycle-shift registers instead of dual-port RAMs, reducing the encoder's complexity and hardware resource consumption. The check-node updated module of the decoder had a new structure and could update without caculating the inputs'absolute values. The synthesis and simulation results showed that the encode speed was 1.8Gbps and the decode speed was about 120Mbps.
Keywords/Search Tags:LDPC, PEG, Subsection Normalized Min-Sum, FPGA
PDF Full Text Request
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