Research On LDPC Coding And Decoding Technology And Its Hardware Implementation

With the continuous development of 5G New Radio Access(NR),the demand for high capacity,low latency,high reliability,high speed and low power communication is more urgent.In the digital communication system,channel coding is one of the key technologies of 5G NR,and massive data transmission requires higher 5G channel coding.Low Density Parity Check(LDPC)codes will continue to play an indispensable role as the long and short coding scheme of data channel in 5G NR channel coding.This paper mainly studies the LDPC coding and decoding algorithm and the hardware design and implementation of the coding and decoding technology.Firstly,we propose the Neural Normalized Min Sum(NNMS)decoding algorithm,which is based on the model driven deep neural network.It combines the advantages of the model driven deep learning method with the traditional NMS decoder,and develops the iterative decoding process between the check node message processing and the variable node message processing into the forward propagation network.The proposed NNMS outperforms up to 1.5d B with fewer iterations compared with the conventional LDPC decoder.Considering that NNMS improves the BER performance at the cost of a large number of multipliers,we propose Shared Neural Normalized Min Sum(SNNMS)improved decoding algorithm to reduce the number of correction factors by sharing neurons,which improves the BER performance without increasing too much computational complexity.What's more,compared with NNMS,its BER performance is improved by 0.4db.With regard to the hardware design and implementation of LDPC coding and decoding technology,considering the realizability and performance of hardware,this paper chooses efficient algorithm and normalized minimum sum algorithm which are more suitable for hardware implementation,and designs and implements LDPC coder and decoder based on the platform of FPGA.In order to verify the correctness and stability of the design,a set of LDPC coding communication system was designed and built based on the KC705 development board of Xilinx,and the transmitter and receiver were jointly adjusted.Finally,the design and function simulation of the LDPC encoding and decoding scheme based on FPGA and the verification of board level were verified.