Research And Design Of High-Rate QC-LDPC Decoder

With the development of the information technology,a large number of Internet applications have emerged,and the amount of network data has greatly increased.People have higher requirements for the reliability and efficiency of communication.As a representative of the third generation forward error correction technology,LDPC has excellent performance close to the Shannon limit,and its coding algorithm is simple and flexible.It has become a research and application hotspot,and is accepted by 3GPP as the code for eMBB data channels in 5G communication.As a subclass of LDPC,QC-LDPC not only inherits excellent performance of LDPC,but also can further reduce the complexity of coding and decoding with its special structure.This makes QC-LDPC widely applied in communication systems and related applications.The optimization and hardware implementation of QC-LDPC decoding algorithm are studied in this thesis.In terms of the algorithm research,two improved algorithms C1 EF and NALA are proposed,based on the special characteristics of the layered decoding algorithm,.When the decoding termination condition triggers,C1 EF utilizes(1120,840)QC-LDPC code special structure,by correcting errors from some variable nodes,to improve the decoding performance.The NALA accelerates the transmittion of information between layers,so that more new information can participate in check-node-update operation,thus achieving improved performance.The simulation results show that the decoding performance of the two improved algorithms is significantly improved than that of the original algorithm.In terms of hardware implementation,this thesis completed the overall structure design of QC-LDPC layered decoder.Input and output buffer module,variable information storage module,check node information storage module and parity check update module are included.RTL is designed by HDL based on this structure.Design,simulation and implement are completed by Xilink's Vivado.Finally,the synthesis and timing report are given.The results show that the decoder can work at 125 MHz and function correctly.